DP83950B datasheet(78/80 Pages) NSC

78 / 80 page

90 AC and DC Specifications (Continued)

TLF11096 – 34

Number

Symbol

Parameter

Min

Max

Units

T90

wradrs

Write Address Setup

T91

wradrh

Write Address Hold

T92

wrabufa

Write Active to BUFEN Active

355

T93

wribufi

Write Inactive to BUFEN Inactive

T94

wradatv

Write Active to Data Valid

275

T95

wrdath

Write Data Hold

T96

wrardya

Write Active to RDY Active

340

585

T97

wrirdyi

Write Inactive to RDY Inactive

T98

wrw

Write Width

600

T99

wradt

Write Active to

350

Data TRI-STATE

Note

Assuming zero propagation delay on external buffer

Note

Minimum high time between readwrite cycles is 100 ns

Note

The data will always TRI-STATE before BUFEN goes active with a load of 100 pF on the data bus

Note

When RDY is used the minimum 600 ns write width does not have to be maintained

100 AC Timing Test Conditions

All specifications are valid only if the mandatory isolation is

employed and all differential signals are taken to be at the

AUI side of the pulse transformer

Input Pulse Levels (TTLCMOS)

GND to 30V

Input Rise and Fall Times (TTLCMOS)

5 ns

Input and Output Reference

Levels (TTLCMOS)

15V

Input Pulse Levels (Diff)

20 VP-P

Input and Output

50% Point of

Reference Levels (Diff)

the Differential

TRI-STATE Reference Levels

Float (DV) g05V

Output Load (See

Figure Below)

TLF11096 – 36

Note 1

100 pF includes scope and jig capacitance

Note 2

S1 e Open for timing tests for push pull outputs

S1 e VCC for VOL test

S1 e GND for VOH test

S1 e VCC for High Impedance to active low and

active low to High Impedance

measurements

S1 e GND for High Impedance to active high and

active high to High Impedance

measurements

DP83950B Datasheet(PDF) 78 Page - National Semiconductor (TI)

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