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MB9B160L Datasheet(PDF) 1 Page - Cypress Semiconductor |
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MB9B160L Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 118 page ![]() MB9B160L Series 32-Bit ARM ® Cortex® - M4F FM4 Microcontroller Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 408-943-2600 Document Number: 002-04976 Rev.*A Revised May 12, 2016 Devices in the MB9B160L Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the ARM ® Cortex®-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I 2C, LIN). Features 32-bit ARM ® Cortex®-M4F Core Processor version: r0p1 Up to 160 MHz Frequency Operation FPU built-in Support DSP instruction Memory Protection Unit (MPU): improves the reliability of an embedded system Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] These series are based on two independent on-chip Flash memories. MainFlash memory Up to 512 Kbytes Built-in Flash Accelerator System with 16 Kbytes trace buffer memory The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System. Security function for code protection WorkFlash memory 32 Kbytes Read cycle: • 6wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz • 4wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz • 2wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz • 0wait-cycle: the operation frequency up to 40 MHz Security function is shared with code protection [SRAM] This is composed of three independent SRAMs (SRAM0, SRAM1, and SRAM2). SRAM0 is connected to I-code bus and D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core. SRAM0: Up to 32 Kbytes SRAM1: Up to 16 Kbytes SRAM2: Up to 16 Kbytes Multi-function Serial Interface (Max 6 channels) 64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication mode or bit length.) Operation mode is selectable from the followings for each channel. UART CSIO LIN I 2C UART Full-duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4) Various error detect functions available (parity errors, framing errors, and overrun errors) CSIO Full-duplex double buffer Built-in dedicated baud rate generator Overrun error detect function available Serial chip select function (ch.6 only) Supports high-speed SPI (ch.0 and ch.6 only) Data length 5 to 16-bit LIN LIN protocol Rev.2.1 supported Full-duplex double buffer Master/Slave mode supported LIN break field generation (can change to 13 to 16-bit length) LIN break delimiter generation (can change to 1 to 4-bit length) |
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