CS2

SS

20 PA

1 PA

LM5025A

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SNVS293E – DECEMBER 2004 – REVISED MARCH 2013

A small RC filter, located near the controller, is recommended for each of the CS pins. The CS1 input has an

internal FET which discharges the current sense filter capacitor at the conclusion of every cycle, to improve

dynamic performance. This same FET remains on an additional 50ns at the start of each main switch cycle to

attenuate the leading edge spike in the current sense signal. The CS2 discharge FET only operates following a

CS2 event, UVLO and thermal shutdown.

The LM5025A CS comparators are very fast and may respond to short duration noise pulses. Layout

considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS

filter must be placed very close to the device and connected directly to the pins of the IC (CS and GND). If a

current sense transformer is used, both leads of the transformer secondary should be routed to the filter

network , which should be located close to the IC. If a sense resistor in the source of the main switch MOSFET is

used for current sensing, a low inductance type of resistor is required. When designing with a current sense

resistor, all of the noise sensitive low power ground connections should be connected together near the IC GND

and a single connection should be made to the power ground (sense resistor ground point).

Figure 15. Current Limit

Oscillator and Sync Capability

The LM5025A oscillator is set by a single external resistor connected between the RT pin and GND. To set a

desired oscillator frequency (F), the necessary RT resistor can be calculated from:

RT = (5725/F)

1.026

(3)

where F is in kHz and RT in k

Ω.

The RT resistor should be located very close to the device and connected directly to the pins of the IC (RT and

GND).

A unique feature of LM5025A is the ability to synchronize the oscillator to an external clock with a frequency that

is either higher or lower than the frequency of the internal oscillator. The lower frequency sync frequency range is

80% of the free running internal oscillator frequency. There is no constraint on the maximum SYNC frequency. A

minimum pulse width of 100ns is required for the synchronization clock . If the synchronization feature is not

required, the SYNC pin should be connected to GND to prevent any abnormal interference . The internal

oscillator can be completely disabled by connecting the RT pin to REF. Once disabled, the sync signal will act

directly as the master clock for the controller. Both the frequency and the maximum duty cycle of the PWM

controller can be controlled by the SYNC signal (within the limitations of the Volt x Second Clamp). The

maximum duty cycle (D) will be (1-D) of the SYNC signal.

Feed-Forward Ramp

signal. The slope of the signal at the RAMP pin will vary in proportion to the input line voltage. This varying slope

provides line feedforward information necessary to improve line transient response with voltage mode control.

The RAMP signal is compared to the error signal at the COMP pin by the pulse width modulator comparator to

control the duty cycle of the main switch output. The Volt Second Clamp comparator also monitors the RAMP pin

and if the ramp amplitude exceeds 2.5V the present cycle is terminated. The ramp signal is reset to GND at the

end of each cycle by either the internal clock or the Volt Second comparator, which ever occurs first.

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