DP83865 datasheet(7/86 Pages) NSC

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1.0 Pin Description (Continued)

1.2 Management Interface

1.3 Media Dependent Interface

1.4 JTAG Interface

Signal Name

Type

PQFP

Pin #

Description

MDC

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial man-

agement input/output data. This clock may be asynchronous to the MAC trans-

mit and receive clocks. The maximum clock rate is 2.5 MHz and no minimum.

MDIO

I/O

MANAGEMENT DATA I/O: Bi-directional management instruction/data signal

that may be sourced by the management station or the PHY. This pin requires

a 2k

Ω pullup resistor.

INTERRUPT

O_Z,

MANAGEMENT INTERRUPT: It is an active-low open drain output indicating

to the MAC layer or to a managment interface that an interrupt has requested.

The interrupt status can be read through the Interrupt Status Register. (See

section “3.15 Interrupt” on page 47.)

If used this pin requires a 2k

Ω pullup resistor. This pin is to be left floating if it

is not used.

Signal Name

Type

PQFP

PIn #

Description

MDIA_P

MDIA_N

MDIB_P

MDIB_N

MDIC_P

MDIC_N

MDID_P

MDID_N

I/O

108

109

114

115

120

121

126

127

Media Dependent Interface: Differential receive and transmit signals.

The TP Interface connects the DP83865 to the CAT-5 cable through a single

common magnetics transformer. These differential inputs and outputs are con-

figurable to 10BASE-T, 100BASE-TX or 1000BASE-T signalling:

The DP83865 will automatically configure the driver outputs for the proper sig-

nal type as a result of either forced configuration or Auto-Negotiation. The au-

tomatic MDI / MDIX configuration allows for transmit and receive channel

configuration and polarity configuration between channels A and B, and C and

NOTE: During 10/100 Mbps operation only MDIA_P, MDIA_N, MDIB_P and

MDIB_N are active. MDIA_P and MDIA_N are transmitting only and MDIB_P

and MDIB_N are receiving only. (See section “3.5 Auto-MDIX resolution” on

page 44)

Signal Name

Type

PQFP

PIn #

Description

TRST

I, PD

TEST RESET: IEEE 1149.1 Test Reset pin, active low reset provides for asyn-

chronous reset of the Tap Controller. This reset has no effect on the device

registers.

This pin should be pulled down through a 2k

Ω resistor if not used.

TDI

I, PU

TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned

into the device via TDI.

This pin should be left floating if not used.

TDO

TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent

test results are scanned out of the device via TDO.

This pin should be left floating if not used.

TMS

I, PU

TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin se-

quences the Tap Controller (16-state FSM) to select the desired test instruc-

tion.

This pin should be left floating if not used.

DP83865 Datasheet(PDF) 7 Page - National Semiconductor (TI)

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