DP83865 datasheet(8/86 Pages) NSC

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1.0 Pin Description (Continued)

1.5 Clock Interface

1.6 Device Configuration and LED Interface

(See section “3.7 PHY Address, Strapping Options and LEDs” on page 45 and section “5.9 LED/Strapping Option” on

page 67.)

TCK

TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test

logic input and output controlled by the testing entity.

This pin should be left floating if not used.

Signal Name

Type

PQFP

Pin #

Description

CLK_IN

CLOCK INPUT: 25 MHz oscillator or crystal input (50 ppm).

CLK_OUT

CLOCK OUTPUT: Second terminal for 25 MHz crystal. Must be left floating if

a clock oscillator is used.

CLK_TO_MAC

CLOCK TO MAC OUTPUT: This clock output can be used to drive the clock

input of a MAC or switch device. This output is available after power-up and is

active during all modes except during hardware or software reset. Note that the

clock frequency is selectable through CLK_MAC_FREQ between 25 MHz and

125 MHz.

To disable this clock output the MAC_CLK_EN_STRAP pin has to be tied low.

Signal Name

Type

PQFP

Pin #

Description

NON_IEEE_STRAP

I/O,

S, PD

NON IEEE COMPLIANT MODE ENABLE: This mode allows interoperability

with certain non IEEE compliant 1000BASE-T transceivers.

‘1’ enables IEEE compliant operation and non-compliant operation

‘0’ enables IEEE compliant operation but inhibits non-compliant operation

Note: The status of this bit is reflected in bit 10 of register 0x10. This pin also

sets the default for and can be overwritten by bit 9 of register 0x12.

MAN_MDIX_STRAP /

TX_TCLK

I/O,

S, PD

MANUAL MDIX SETTING: This pin sets the default for manual MDI/MDIX

configuration.

‘1’ PHY is manually set to cross-over mode (MDIX)

‘0’ PHY is manually set to straight mode (MDI)

Note: The status of this bit is reflected in bit 8 of register 0x10. This pin also

sets the default for and can be overwritten by bit 14 of register 0x12.

TX_TCLK: TX_TCLK is enabled by setting bit 7 of register 0x12. It is used to

measure jitter in Test Modes 2 and 3 as described in IEEE 802.3ab specifica-

tion. TX_TCLK should not be confused with the TX_CLK signal. See Table 12

on page 29 regarding Test Mode setting. This pin should be left floating if not

used.

Signal Name

Type

PQFP

PIn #

Description

DP83865 Datasheet(PDF) 8 Page - National Semiconductor (TI)

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