LP2996A

GND

472F

+

+

+

2202F

SD

SD

0.012F

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LP2996A

SNOSCY7 – JUNE 2014

LP2996A DDR Termination Regulator

1 Features

3 Description

The LP2996A linear regulator is designed to meet the

1

•

JEDEC SSTL-2 specifications for termination of DDR-

•

Source and Sink Current

SDRAM. The device also supports DDR2, DDR3 and

•

Low Output Voltage Offset

The

device

contains

a

high-speed

operational

•

No External Resistors Required

amplifier to provide excellent response to load

•

Linear Topology

transients. The output stage prevents shoot through

•

Suspend to Ram (STR) Functionality

while delivering 1.5A continuous current and transient

peaks up to 3A in the application as required for

•

Low External Component Count

DDR-SDRAM

termination.

The

LP2996A

also

•

Thermal Shutdown

•

LP2998/8Q recommended for -40°C to 125°C

chipset and DIMMs.

2 Applications

An additional feature found on the LP2996A is an

•

DDR1, DDR2, DDR3, and DDR3L Termination

active low shutdown (SD) pin that provides Suspend

Voltage

To RAM (STR) functionality. When SD is pulled low

the

•

FPGA

•

Industrial/Medical PC

power savings advantage can be obtained in this

•

SSTL-2 and SSTL-3 Termination

mode through lower quiescent current.

•

HSTL Termination

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

LP2996A

SO PowerPAD (8)

4.89 mm x 3.90 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Simplified Schematic

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.