LP3913 datasheet(50/70 Pages) TI1

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LP3913

SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013

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LDO2 Control Register (09)h

D7–6

D4–0

Access

Read Only 0

R/W

Data

Reserved

Operation

LDO1 Output Voltage (V)

0: enable/ disable

5’h00

1.3

determined by

5’h01

1.4

state of LDO2EN

5’h02

1.5

1: enable,

5’h03

1.6

override LDO2EN

state

5’h04

1.7

5’h05

1.8

5’h06

1.9

5’h07

2.0

5’h08

2.1

5’h09

2.2

5’h0A

2.3

5’h0B

2.4

5’h0C

2.5

5’h0D

2.6

5’h0E

2.7

5’h0F

2.8

5’h10

2.9

5’h11

3.0

5’h12

3.1

5’h13

3.2

5’h14 –5’h1F

3.3

Reset

n/a

5’h14

BUCK1, BUCK2: Synchronous Step Down Magnetic DC/DC Converters

Functional Description

The LP3913, incorporates two high efficiency synchronous switching buck regulators, BUCK1 and BUCK2 that

deliver a constant voltage from a single Li-Ion battery to the portable system processors, Memory and I/O. Using

a voltage mode architecture with synchronous rectification, both bucks have the ability to deliver up to 600 mA

depending on the input voltage and output voltage (voltage head room), and the inductor chosen (maximum

current capability).

There are three modes of operation depending on the current required: PWM, PFM, and shutdown. PWM mode

handles current loads of approximately 70 mA or higher, delivering voltage precision of ±3% with 90% efficiency

or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current

consumption (IQ = 15 µA typ.) and a longer battery life. The Standby operating mode turns off the device, offering

the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be forced

through the setting of the buck control register.

Both BUCK1 and BUCK2 can operate up to a 100% duty cycle (PMOS switch always on). Additional features

include soft-start, under-voltage lock-out, current overload protection, and thermal overload protection.

Circuit Operation Description

A buck converter contains a control block, a switching PFET connected between input and output, a synchronous

rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first

portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow

from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a

ramp with a slope of VIN-VOUT/L.

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