DS3875 datasheet(4/58 Pages) NSC

4 / 58 page

Pin Definition

of Pins

Type

Description

SIGNAL TOFROM THE HANDSHAKE TRANSCEIVER

APO

Arbitration handshake signal from the controller

AQO

Arbitration handshake signal from the controller

ARO

Arbitration handshake signal from the controller

AC0O

Arbitration condition signal from the controller

AC1O

Arbitration condition signal from the controller

API

Arbitration handshake signal from Futurebusa This signal is the filtered and inverted version

of the Futurebusa backplane signal AP

AQI

Arbitration handshake signal from Futurebusa This signal is the filtered and inverted version

of the Futurebusa backplane signal AQ

ARI

Arbitration handshake signal from Futurebusa This signal is the filtered and inverted version

of the Futurebusa backplane signal AR

AC0I

Arbitration condition signal from Futurebusa

AC1I

Arbitration condition signal from Futurebusa

SIGNAL TOFROM THE ARBITRATION TRANSCEIVER

(Note These pins are mapped tofrom the DS3885 Futurebusa

Arbitration Transceiver)

CN(70)

The bus to carry competition number tofrom the arbitration transceiver

CNp

Parity bit of the competition number

CMPT

Enables the Arbitration number onto Futurebusa

Direction control for the competition number bus tofrom the transceiver

Latch enable for latching the Arbitration number from the controller into the transceiver

PER

PARITY ERROR

Indicates that a parity error was detected on the winner’s arbitration number

WIN

Win signal when competinggreater than signal when not competing (used to preempt)

ALL1

Indicates that all the arbitration number lines on the bus are asserted (used for messages)

SIGNALS TOFROM THE PARALLEL PROTOCOL CONTROLLER

BRQ

BUS REQUEST

Indicates to the controller to acquire the bus for the module’s use

BGRNT

BUS GRANT

Signal asserted by the controller after the detection of a bus request The

module can start using the bus

RINT

Will put the arbitration controller in phase 0 and release all the bus lines except AR

selective reset is performed The rising edge will release controller from phase 0 This reset is

to be used for bus initialization

RST

Reset signal from the host An internal reset is performed All bus signals are released The

rising edge will put the controller in phase 0 (same as power-up reset)

HALT

Will halt the arbitration controller in phase 0 This signal is for use during live insertion

ENDT

END OF TENURE

Indicates the true end of bus tenure of the current master This line may be

asserted only after all the parallel protocol lines are released (Generated via external logic

from BRQ released)

DS3875 Datasheet(PDF) 4 Page - National Semiconductor (TI)

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