DS3875 datasheet(12/58 Pages) NSC

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40 DS3875 Interfaces (Continued)

The input signal ALL1 (AB 7

and ABp all asserted)

is used to determine if any module is sending an arbitration

message during pass 1 For convenience the Arbitration

Controller outputs FSTR (to an external FIFO) during mes-

sage reception so more than one arbitration message may

be stored by the module

The Arbitration Controller has dedicated interrupt pins

(ERINT

MGINT

PFINT ) that interface with the Protocol

Controller so that important messages and error indications

can be quickly detected

The Protocol Controller will issue the message request or

bus request signals to the DS3875 When a message has

been transmitted (Second Pass of arbitration Phase 5) the

Arbitration Controller will assert MGTX

On board reset initialization power-up and live insertion

logic will inform the Arbitration Controller which type of reset

operation to perform Power-Up Reset (RST ) Initialization

(RINT ) or live insertion (HALT ) See Sections 100 and

110 for more information

50 Arbitrating for Futurebusa

The arbitration process allows a module to seek and gain

tenure of Futurebusa to transfer data to or from another

module The arbitration process is independent of the data

transfer process and may take place concurrently with data

transactions on Futurebusa If a module (or several mod-

ules) want to use the bus an arbitration competition takes

place The module with the highest arbitration number gets

tenure of the bus

The National Semiconductor solution to Futurebusa arbi-

tration includes the DS3875 Arbitration Controller

the

DS3885 Arbitration Transceiver and the DS3884 Hand-

shake Transceiver (see front page system block diagram)

More information on Arbitration as it applies to the Future-

busa IEEE standard is available in Section 5 of the ‘‘Futu-

rebusa P8961 Logical Layer Specification’’

51 UNRESTRICTEDRESTRICTED MODES OF

OPERATION

The Arbitration Controller supports either the Unrestricted

or the Restricted mode of arbitration In the system environ-

ment all modules must be configured to operate in the

same mode at any given time

During initialization the Unrestricted mode is set since it

must be supported by all modules The Unrestricted mode

allows a single pass of an 8-bit arbitration number or a two

pass of a 16-bit arbitration number to be used

Futurebusa allows arbitration numbers requiring a single

pass control acquisition cycle to be mixed with those requir-

ing a two pass control acquisition cycle During the first pass

of a two pass cycle more than one module may have the

same number however during the second pass only one

winner results where the competition numbers must be

unique A logic zero in the RU

bit of the CTRL2 register

selects the unrestricted mode

The Restricted mode of operation is optional and is selected

by setting the RU

bit to a logic one in the CTRL2 register

This mode limits arbitration numbers to 8 bits Thus only a

single control acquisition cycle occurs where all numbers

are unique The arbitration numbers are assigned by the

module and can be dynamically changed

52 THE ARBITRATION NUMBER AND ARBITRATION

CIRCUIT

Each module has a unique arbitration number When two or

more modules compete for the bus the module with the

highest arbitration number will win the competition

The DS3885 Arbitration Transceiver contains the arbitration

circuit See

Figure 4 for a functional model of the arbitration

circuit A Parallel Contention Arbitration Protocol controls

how modules assert and release the AB 7

and

ABp

After a period of time (ta) the protocol ensures that

only the winners arbitration number will remain on the

AB 7

and ABp

The arbitration number consists of one or two competition

numbers CN(7

0) The Arbitration Controller Transmits

Receives the competition number tofrom the Arbitration

Transceiver The CN

signal latches the competition

number into the transceiver while the AB

signal al-

lows the controller to read in the winner’s competition num-

ber Along with the competition number the Arbitration Con-

troller transmits the CNp bit the generated parity bit of the

competition number to the Arbitration Transceiver Odd

parity as specified in the Futurebusa specifications is im-

plemented Thus CNp is set when even number of ones are

present in the competition number When CN(7

0) is

received from the Arbitration Transceiver the PER

bit is

checked for error detection

Referring to Table II in the Unrestricted mode the CN7 bit

indicates if the module requires another arbitration pass

When a one pass and a two pass arbitration number occur

in the same control acquisition cycle the one pass arbitra-

tion number will win

The DS3875 allows the module to dynamically change the

arbitration number by writing into the TXCN0 andor the

TXCN1 registers (see Section 7) If the arbitration number is

changed during an arbitration cycle it will be used in the next

arbitration competition

The arbitration number is composed of three fields Priority

Field Round Robin Field and a Unique Field

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