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TLV320AIC21 Datasheet(PDF) 15 Page - Texas Instruments |
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TLV320AIC21 Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 56 page  www.ti.com SDA SCL tf tLOW tHD;STA tHD;DAT tHIGH tSU;STA tSU;STO tBUF tr tHD;STA tf tSU;DAT tr TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363D – MARCH 2002 – REVISED APRIL 2005 Figure 3. I2C / S2C Timing Diagram PARAMETER SYMBOL MIN MAX UNIT SCL clock frequency tSCL 0 900 kHz Hold time (repeated START condition. After this period, the first clock pulse is tHD;STA 100 generated. Low period of the SCL clock tLOW 560 High period of the SCL clock tHIGH 560 Set-up time for a repeated START condition tSU;STA 100 Data hold time tHD;DAT 50 ns Data set-up time tSU;DAT 50 Rise time of both SDA and SCL signals tr 300 Fall time of both SDA and SCL signals tf 100 Set-up time for STOP condition tSU;STO 100 Bus free time between a STOP and START condition tBUF 500 15 |
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