UCD3138128APFC datasheet(37/83 Pages) TI1

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UCD3138128A

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SLUSC99 – JULY 2016

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6 = DPWMC(n+1)

7 = DPWMC(n+2)

8 = DPWMC(n+3)

The DPWM number wraps around just like the Edge Gen unit. For DPWM3 the following definitions apply:

DPWM(n)

DPWM3

DPWM(n+1)

DPWM0

DPWM(n+2)

DPWM1

DPWM(n+3)

DPWM2

9.3.5 Synchronous Rectifier MOSFET Ramp And IDE Calculation

The device has built in logic for optimizing the performance of the synchronous rectifier MOSFETs. This comes in

two forms:

•

Synchronous Rectifier MOSFET ramp for softly turning on and off the MOSFETs

•

Ideal Diode Emulation (IDE) calculation

When starting up a power supply, It is not uncommon for there to already be a voltage present on the output –

this is called pre-bias. It can be very difficult to calculate the ideal synchronous rectifier MOSFET on-time for this

case. If it is not calculated correctly, it may pull down the pre-bias voltage, causing the power supply to sink

current. To avoid this, the synchronous rectifier MOSFETs are not turned on until after the power supply has

ramped up to the nominal output voltage. The synchronous rectifier MOSFETs are then turned on slowly in order

to avoid an output voltage glitch. The synchronous rectifier MOSFET ramp logic can be used to turn them on at a

rate well below the bandwidth of the filter.

In discontinuous mode, the ideal on-time for the synchronous rectifier MOSFETs is a function of Vin, Vout, and the

primary side duty cycle (D). The IDE logic in the UCD3138xA takes Vin and Vout data from the firmware and

combines it with D data from the filter hardware. It uses this information to calculate the ideal on-time for the

synchronous rectifier MOSFETs.

9.3.6 Filter

The UCD3138xA filter is a PID filter with many enhancements for power supply control. Some of its features

include:

•

Traditional PID Architecture

•

Programmable non-linear limits for automated modification of filter coefficients based on received EADC error

•

Multiple coefficient sets fully configurable by firmware

•

Full 24-bit precision throughout filter calculations

•

Programmable clamps on integrator branch and filter output

•

Ability to load values into internal filter registers while system is running

•

Ability to stall calculations on any of the individual filter branches

•

Ability to turn off calculations on any of the individual filter branches

•

Duty cycle, resonant period, or phase shift generation based on filter output.

•

Flux balancing

•

Voltage feed forward

Here is the first section of the Filter :

UCD3138128APFC Datasheet(PDF) 37 Page - Texas Instruments

UCD3138128APFC Datasheet(HTML) 37 Page - Texas Instruments

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