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TMS320C6421 Datasheet(PDF) 83 Page - Texas Instruments |
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TMS320C6421 Datasheet(HTML) 83 Page - Texas Instruments |
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83 / 222 page  3.7.2.2 PINMUX1 Register Description TMS320C6421 Fixed-Point Digital Signal Processor www.ti.com SPRS346D – JANUARY 2007 – REVISED JUNE 2008 Table 3-17. PINMUX0 Register Bit Descriptions (continued) Bit Field Name Description Pins Controlled EM_D[7]/GP[21] EM_D[6]/GP[20] EM_D[5]/GP[19] EM_D[4]/GP[18] EM_D[3]/GP[17] EM_D[2]/GP[16] EM_D[1]/GP[15] EM_D[0]/GP[14] EM_R/WGP[35] EMIFA Pinout Modes EM_A[21]/GP[34] This field does not affect the actual EMIFA operation. It only determines what EM_A[20]/GP[44] multiplexed pins in the EMIFA Block serves as EMIFA pins. EM_A[19]/GP[45] EM_A[18]/GP[46] 000b = No EMIFA Mode EM_A[17]/GP[47] None of the multiplexed pins in the EMIFA Block serves as EMIFA pins. They EM_A[16]/GP[48] serve as GPIO pins. EM_A[15]/GP[49] EM_A[14]/GP[50] 001b = Reserved. EM_A[13]/GP[51] 010b = 8-bit EMIFA (Async) Pinout Mode 2 EM_A[12]/GP[89] Pinout allows up to a maximum of these functions from EMIFA Block: 8-bit EMIFA EM_A[11]/GP[90] 2:0 AEM(1) (Async or NAND) + GPIO + EMAC(RMII). All of the pins listed under the "Pins EM_A[10]/GP[91] Controlled" column serve as EMIFA pins. PINMUX0.RMII can be set to 0 or 1. EM_A[9]/GP[92] EM_A[8]/GP[93] 011b = Reserved. EM_A[7]/GP[94] EM_A[6]/GP[95] 100b = Reserved. EM_A[5]/GP[96] EM_A[4]/GP[10]/(PLLMS2) 101b = 8-bit EMIFA (NAND) Pinout Mode 5 EM_A[3]/GP[11] Pinout allows up to a maximum of these functions from EMIFA Block: 8-bit EMIFA EM_A[2]/(CLE)/GP[8]/(PLLMS0) (NAND) + GPIO + EMAC(RMII). PINMUX0.RMII can be set to 0 or 1. EM_A[1]/(ALE)/GP[9]/(PLLMS1) 110b through 111b = Reserved. EM_A[0]/GP[7]/(AEM2) EM_CS2/GP[12] EM_BA[0]/GP[6]/(AEM1) EM_BA[1]/GP[5]/(AEM0) The pin mux for these pins are controlled by a combination of AEM and other fields. For the full set of valid configurations of these pins, see Section 3.7.3.11.2, EMIFA Block Pin-by-Pin Multiplexing Summary. (1) The AEM default value is latched at reset from AEM[2:0] configuration inputs. The latched values are also shown at BOOTCFG.DAEM (read-only). The Pin Multiplexing 1 Register (PINMUX1) controls the pin multiplexing of all Pin Mux Blocks. The PINMUX1 register format is shown in Figure 3-12 and the bit field descriptions are given in Table 3-18. Some muxed pins are controlled by more than one PINMUX bit field. For the combination of PINMUX bit fields that control each muxed pin, see Section 3.7.3.1, Multiplexed Pins on C6421. 31 26 25 24 23 22 21 20 19 18 17 16 RESERVED SPBK1 SPBK0 TIM1BK RSV TIM0BK R/W-0000 00 R/W-00 R/W-00 R/W-00 R/W-00 R/W-00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM1B CKOBK RSV UR0FCBK RSV UR0DBK RSV HOSTBK RESERVED RSV K R/W-01 R/W-0 R/W-0 R/W-00 R/W-0 R/W-0 R/W-0 R/W-000 R/W-000 R-0 LEGEND: R/W = Read/Write; R = Read only; P = specified pin state; -n = value after reset (1) For proper C6421 device operation, always write a value of "0" to all RESERVED/RSV bits. Figure 3-12. PINMUX1 Register—0x01C4 0004 (1) Submit Documentation Feedback Device Configurations 83 |
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