TMS320C6421 datasheet(11/222 Pages) TI1

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2.2.1.1 L1P Configuration Register (L1PCFG) Description

TMS320C6421

Fixed-Point Digital Signal Processor

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SPRS346D – JANUARY 2007 – REVISED JUNE 2008

The L1P is divided into two regions—denoted as L1P Region 0 and L1P Region 1. This is the L1P

architecture on the C6421:

• L1P Region 0: 0-KByte Memory

• L1P Region 1: 16-KByte Memory

–

L1P Region 1 can be configured as mapped memory or cache and has a 0 wait state latency. This

region is shown as "L1P RAM/Cache" in Table 2-5, Memory Map Summary.

The C6421 does not support memory protection on L1P.

The L1D is divided into two regions—denoted as L1D Region 0 and L1D Region 1. This is the L1D

architecture on the C6421:

• L1D Region 0: 16-KByte Memory

–

This region is shown as "L1D RAM" in Table 2-5, Memory Map Summary.

• L1D Region 1: 32-KByte Memory

–

L1D Region 1 can be configured as mapped memory or cache. This region is shown as "L1D

RAM/Cache" in Table 2-5, Memory Map Summary.

The C6421 does not support memory protection on L1D.

L2 memory implements two separate memory ports. This is the L2 architecture on the C6421:

• Port 0

–

This port is shown as "L2 RAM/Cache" in Table 2-5, Memory Map Summary.

–

Banking Scheme: 2 x 128-bit banks

–

Latency: 1 cycle (0 wait state)

• Port 1

–

This port is shown as "Boot ROM" in Table 2-5, Memory Map Summary.

–

Banking Scheme: 1 x 256-bit bank

–

Latency: 1 cycle (0 wait state)

The C6421 does not support memory protection on L2.

For more detailed information about the C64x+ Cache Memory Architecture, see the TMS320C64x+ DSP

Cache User's Guide (literature number SPRU862) and the TMS320C64x+ DSP Megamodule Reference

Guide (literature number SPRU871).

The L1P Configuration Register (L1PCFG) controls/defines the size of the L1P cache. On the C6421, the

L1PCFG register is device-specific and varies from what is shown in the TMS320C64x+ DSP

Megamodule Reference Guide (literature number SPRU871). The format and bit field descriptions of the

L1PCFG register for the C6421 are shown in Figure 2-2 and Table 2-3, respectively.

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