TMS570LS0332PZ datasheet(84/110 Pages) TI1

84 / 110 page

TMS570LS0432, TMS570LS0332

SPNS186B – OCTOBER 2012 – REVISED JUNE 2015

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7.7

Multibuffered / Standard Serial Peripheral Interface

The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of

programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.

Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display

drivers, and ADCs.

7.7.1

Features

Both Standard and MibSPI modules have the following features:

•

16-bit shift register

•

Receive buffer register

•

11-bit baud clock generator

•

SPICLK can be internally generated (master mode) or received from an external clock source (slave

mode)

•

Each word transferred can have a unique format

•

SPI I/Os not used in the communication can be used as digital input/output signals

Table 7-11. MibSPI/SPI Default Configurations

MibSPIx/SPIx

I/Os

MibSPI1

MIBSPI1SIMO[0], MIBSPI1SOMI[0], MIBSPI1CLK, MIBSPI1nCS[3:0], MIBSPI1nENA

SPI2

SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[0]

SPI3

SPI3SIMO, SPI3SOMI, SPI3CLK, SPI3nENA, SPI3nCS[0]

7.7.2

MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of four parts:

a 16-bit transmit field, a 16-bit receive field, a 16-bit control field, and a 16-bit status field. The Multibuffer

RAM can be partitioned into multiple transfer group with variable number of buffers each.

7.7.3

MibSPI Transmit Trigger Events

Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event

and a trigger source can be chosen. A trigger event can be, for example, a rising edge or a permanent low

level at a selectable trigger source. Up to 15 trigger sources are available which can be used by each

transfer group. These trigger options are listed in Table 7-12.

Peripheral Information and Electrical Specifications

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