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TMS320UC5409 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320UC5409 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 81 page  TMS320UC5409 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS101E − APRIL 1999 − REVISED OCTOBER 2008 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus D 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators D 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation D Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator D Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle D Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) D Data Bus With a Bus-Holder Feature D Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space D 16K x 16-Bit On-Chip ROM D 32K x 16-Bit Dual-Access On-Chip RAM D Single-Instruction-Repeat and Block-Repeat Operations for Program Code D Block-Memory-Move Instructions for Better Program and Data Management D Instructions With a 32-Bit Long Word Operand D Instructions With Two- or Three-Operand Reads D Arithmetic Instructions With Parallel Store and Parallel Load D Conditional Store Instructions D Fast Return From Interrupt D On-Chip Peripherals − Software-Programmable Wait-State Generator and Programmable Bank Switching − On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source − Three Multichannel Buffered Serial Ports (McBSPs) − Enhanced 8-Bit Parallel Host-Port Interface With 16-Bit Data/Addressing − One 16-Bit Timer − Six-Channel Direct Memory Access (DMA) Controller D Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes D CLKOUT Off Control to Disable CLKOUT D On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1† (JTAG) Boundary Scan Logic D 12.5-ns Single-Cycle Fixed-Point Instruction Execution Time (80 MIPS) D 1.8-V Core Power Supply D 1.8-V to 3.6-V I/O Power Supply Enables Operation With a SIngle 1.8-V Supply or With Dual Power Supplies D Available in a 144-Pin Plastic Thin Quad Flatpack (TQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix) Copyright 2008, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Not Recommended For New Designs |
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