TMS320UC5409 datasheet(10/81 Pages) TI1

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TMS320UC5409

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS101E − APRIL 1999 − REVISED OCTOBER 2008

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTION

I/O†

TERMINAL

NAME

DESCRIPTION

I/O†

OSCILLATOR/TIMER SIGNALS

CLKOUT

O/Z

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is

bounded by rising edges of this signal. CLKOUT also goes into the high-impedance state when OFF is low.

CLKMD1

CLKMD2

CLKMD3

Clock mode select signals. These inputs select the mode that the clock generator is initialized to after reset. The logic

levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized to the

selected mode. After reset, the clock mode can be changed through software, but the clock mode select signals have

no effect until the device is reset again.

X2/CLKIN

Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input.

Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left unconnected.

X1 does not go into the high-impedance state when OFF is low.

TOUT

O/Z

Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT cycle

wide. TOUT also goes into the high-impedance state when OFF is low.

MULTICHANNEL BUFFERED SERIAL PORT SIGNALS

BCLKR0

BCLKR1

BCLKR2

I/O/Z

Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.

BDR0

BDR1

BDR2

Serial data receive input

BFSR0

BFSR1

BFSR2

I/O/Z

Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.

BCLKX0

BCLKX1

BCLKX2

I/O/Z

Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as an

input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when OFF goes

low.

BDX0

BDX1

BDX2

O/Z

Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is asserted,

or when OFF is low.

BFSX0

BFSX1

BFSX2

I/O/Z

Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX can

be configured as an input or an output; it is configured as an input following reset. BFSX goes into the high-impedance

state when OFF is low.

HOST-PORT INTERFACE SIGNALS

A0 – A15

These pins can be used to address internal memory via the HPI when the HPI16 pin is high.

D0 – D15

I/O

These pins can be used to read/write internal memory via the HPI when the HPI16 pin is high. The sixteen data pins,

D0 to D15, are multiplexed to transfer data between the core CPU and external data/program memory, I/O devices,

or HPI in 16-bit mode. The data bus is placed in the high-impedance state when not outputting or when RS or HOLD

is asserted. The data bus also goes into the high-inmpedance state when OFF is low.

The data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus

holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven by

the UC5409, the bus holders keep the pins at the logic level that was most recently driven. The data bus holders of

the UC5409 are disabled at reset, and can be enabled/disabled via the BH bit of the BSCR.

HD0 – HD7

I/O/Z

Parallel bidirectional data bus. These pins can also be used as general-purpose I/O pins when the HPI16 pin is high.

HD0–HD7 is placed in the high-impedance state when not outputting data or when OFF is low. The HPI data bus

includes bus holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus

is not being driven by the UC5409, the bus holders keep the pins at the logic level that was most recently driven. The

HPI data bus holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR.

† I = Input, O = Output, Z = High-impedance, S = Supply

‡ Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,

a buffer is recommended to ensure the VIL and VIH specifications are met.

Not Recommended For New Designs

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