IR2103S datasheet(2/12 Pages) IRF

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IR2103(S)

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Symbol

Definition

Min.

Max.

Units

High side floating absolute voltage

-0.3

625

High side floating supply offset voltage

VB - 25

VB + 0.3

VHO

High side floating output voltage

VS - 0.3

VB + 0.3

VCC

Low side and logic fixed supply voltage

-0.3

VLO

Low side output voltage

-0.3

VCC + 0.3

VIN

Logic input voltage (HIN & LIN )

-0.3

VCC + 0.3

dVs/dt

Allowable offset supply voltage transient

—

V/ns

Package power dissipation @ TA ≤ +25°C

(8 Lead PDIP)

—

1.0

(8 Lead SOIC)

—

0.625

RthJA

Thermal resistance, junction to ambient

(8 Lead PDIP)

—

125

(8 Lead SOIC)

—

200

Junction temperature

—

150

Storage temperature

-55

150

Lead temperature (soldering, 10 seconds)

—

300

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the

recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.

Symbol

Definition

Min.

Max.

Units

High side floating supply absolute voltage

VS + 10

VS + 20

High side floating supply offset voltage

Note 1

600

VHO

High side floating output voltage

VCC

Low side and logic fixed supply voltage

VLO

Low side output voltage

VCC

VIN

Logic input voltage (HIN & LIN )0

VCC

Ambient temperature

-40

125

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-

eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured

under board mounted and still air conditions.

Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip

DT97-3 for more details).

°C

°C/W

°C

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