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TMS570LS3134 Datasheet(PDF) 64 Page - Texas Instruments |
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TMS570LS3134 Datasheet(HTML) 64 Page - Texas Instruments |
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64 / 167 page ![]() TMS570LS3134, TMS570LS2134, TMS570LS2124 SPNS165B – APRIL 2012 – REVISED MAY 2015 www.ti.com Table 6-13. Clock Domain Descriptions (continued) CLOCK SOURCE CLOCK DOMAIN DEFAULT CLOCK SELECTION DESCRIPTION NAME SOURCE REGISTER VCLKA3 VCLK VCLKACON1 • Defaults to VCLK as the source • Frequency can be as fast as HCLK frequency. • Is disabled through the CDDISx registers bit 10 VCLKA3_DIVR VCLK VCLKACON1 • Divided down from the VCLKA3 using the VCLKA3R field of the VCLKACON1 register at address 0xFFFFE140 • Frequency can be VCLKA3/1, VCLKA3/2, ..., or VCLKA3/8 • Default frequency is VCLKA3/2 • Is disabled separately through the VCLKACON1 register VCLKA3_DIV_CDDIS bit only if the VCLKA3 clock is not disabled VCLKA4 VCLK VCLKACON1 • Defaults to VCLK as the source • Is disabled through the CDDISx registers bit 11 RTICLK VCLK RCLKSRC • Defaults to VCLK as the source • If a clock source other than VCLK is selected for RTICLK, then the RTICLK frequency must be less than or equal to VCLK/3 – Application can ensure this by programming the RTI1DIV field of the RCLKSRC register, if necessary • Is disabled through the CDDISx registers bit 6 64 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback |
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