TMS570LS3134 datasheet(89/167 Pages) TI1

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EMIF_CLK

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_DATA[15:0]

2 EM_CLK Delay

BASIC SDRAM

READ OPERATION

EMIF_nCS[0]

EMIF_nDQM[1:0]

EMIF_nRAS

EMIF_nCAS

EMIF_nWE

TMS570LS3134, TMS570LS2134, TMS570LS2124

www.ti.com

SPNS165B – APRIL 2012 – REVISED MAY 2015

Table 6-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued)

NO.

PARAMETER

MIN

NOM

MAX

UNIT

Output setup time,

tsu(EMAV-EMWEL)

EMIFADDR[21:0] valid to

(WS)*E-4

(WS)*E

(WS)*E+3

EMIFnWE low

Output hold time, EMIFnWE high

th(EMWEH-EMAIV)

(WH)*E-4

(WH)*E

(WH)*E+3

to EMIFADDR[21:0] invalid

EMIFnWE active low width (EW

(WST)*E-3

(WST)*E

(WST)*E+3

= 0)

tw(EMWEL)

EMIFnWE active low width (EW

(WST+(EWC*16))*E-3

(WST+(EWC*16))*E

(WST+(EWC*16))* E+3

= 1)

Delay time from EMIFnWAIT

td(EMWAITH-EMWEH)

3E-4

4E+30

deasserted to EMIFnWE high

Output setup time,

tsu(EMDV-EMWEL)

EMIFDATA[15:0] valid to

(WS)*E-4

(WS)*E

(WS)*E+3

EMIFnWE low

Output hold time, EMIFnWE high

th(EMWEH-EMDIV)

(WH)*E-4

(WH)*E

(WH)*E+3

to EMIFDATA[15:0] invalid

Output setup time,

tsu(EMDQMV-EMWEL)

EMIFnDQM[1:0] valid to

(WH)*E-4

(WH)*E

(WH)*E+3

EMIFnWE low

Output hold time, EMIFnWE high

th(EMWEH-EMDQMIV)

(WH)*E-4

(WH)*E

(WH)*E+3

to EMIFnDQM[1:0] invalid

6.14.2.2 Synchronous Timing

Figure 6-17. Basic SDRAM Read Operation

System Information and Electrical Specifications

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TMS570LS3134 Datasheet(PDF) 89 Page - Texas Instruments

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