VT8231 datasheet(94/132 Pages) ETC

94 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-88-

Function 4 Regs - Power Management, SMBus and HWM

7HFKQRORJLHV ,QF

:H &RQQHFW

Offset 54 – Power Well Control ...................................... WO

SMBus Clock Select

SMBus Clock from 14.31818 MHz Divider def

SMBus Clock from RTC 32.768 KHz

STR Power Well Output Gating

Disable ...................................................default

1Enable

SUSC# = 0 for STR

Disable ...................................................default

1Enable

SUSST1# / GPO3 Select (Pin V10)

SUSST1#................................................default

1GPO3

GPO2 / SUSB# Select (Pin W9)

SUSB#....................................................default

1GPO2

Before chip rev C, these definitions were reversed

GPO1 / SUSA# Select (Pin V9)

SUSA# ...................................................default

1GPO1

Before chip rev C, these definitions were reversed

1-0

GPO0 (SLOWCLK) Output Selection (Pin T8)

00 From GPO0 (PMU I/O Rx4C[0])...........default

01 1 Hz

10 4 Hz

11 16 Hz

Offset 55 – USB Wakeup.................................................. RW

7-1

Reserved

........................................ always reads 0

USB Wakeup for STR/STD/Soff

Disable................................................... default

1Enable

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