GS4900B datasheet(49/102 Pages) SEMTECH

49 / 102 page

GS4901B/GS4900B SD Clock and Timing Generator

with GENLOCK

Data Sheet

37703 - 4

December 2009

49 of 102

H_Feedback_Divide represents the numerator of the ratio of the output clock frequency

to the frequency of the H reference signal.

For example, to program a loop bandwidth of 25Hz given a 54MHz video clock and a

reference with a 27MHz video clock and 1716 clocks per line, the following steps are

necessary:

1. Calculate H_Feedback_Divide:

Therefore, H_Feedback_Divide = 1716.

2. Calculate the value for Video_Res_Genlock:

3. Calculate the value for Video_Cap_Genlock:

Therefore, program Video_Res_Genlock = 37 and Video_Cap_Genlock = 16.

NOTE: The value programmed in the Video_Res_Genlock register must be between 32

and 42. The value programmed in the Video_Cap_Genlock register must be greater than

10. These limits define the exact range of loop bandwidth adjustment available.

H _Feedback_D ivide

H_Reference_D ivide

pclkout

Hrefin

pclkout

MHz

Hrefin

1716

MHz

H _Feedback_D ivide

H_Reference_D ivide

-27

1716

∴

Video_Res_G enlock

log

2 625

–

()

1716

()

Video_Cap_G enlock

–

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