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GD25Q32C Datasheet(PDF) 29 Page - ELM Electronics

Part # GD25Q32C
Description  32M-bit Serial Flash
PDF  50 Pages
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Manufacturer  ELM [ELM Electronics]
Direct Link  http://www.elmelectronics.com
Logo ELM - ELM Electronics

GD25Q32C Datasheet(HTML) 29 Page - ELM Electronics

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Rev.1.0
50 -
http://www.elm-tech.com
GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
Figure 23. 64KB Block Erase Sequence Diagram
Command
0 1 2 3 4 5 6 7
D8H
CS#
SCLK
SI
8 9
29 30 31
MSB
2 1 0
24 Bits Address
23 22
7.20. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is used to erase all the data of the chip. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The Chip Erase (CE) command is
entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low
for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low → sending Chip Erase command → CS# goes high. The
command sequence is shown in Figure24. CS# must be driven high after the eighth bit of the command code
has been latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-
timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status
Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed only if all
Block Protect (BP2, BP1 and BP0) bits are 0. The Chip Erase (CE) command is ignored if one or more sectors
are protected.
Figure 24. Chip Erase Sequence Diagram
Command
0 1 2 3 4 5 6 7
60H or C7H
CS#
SCLK
SI
7.21. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption
mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while
the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands.
Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle
currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode
can only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep
Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device
ID (RDI) command. This releases the device from this mode. The Release from Deep Power-Down and Read
Device ID (RDI) command also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the
Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command



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