| Electronic Components Datasheet Search |
|
VT86C926 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
|
|
|||||||||||||||||||||||||||||
VT86C926 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers |
|
3 / 24 page ![]() VIA TECHNOLOGIES, INC.PRELIMINARY VT86C926 3 VT86C926 AMAZON PCI ETHERNET CONTROLLER FEATURES * Single chip Ethernet controller for PCI bus interface * Software compatible to NE2000+, NE2000 * Support 35ns access time SRAM * Integrated 10BaseT TP interface -- Built-in pre-equalization circuitry for transmitter -- smart squelch circuit with programmable threshold for receiver -- Selective Link integrity test and link disable -- Selective polarity detection and correction -- Automatic selection between TP and AUI interfaces * Full IEEE 802.3 AUI interface -- Meet 10Base5 and 10Base2 standards -- Thin-net or Thick-net enable signal * Jumper or Jumperless configuration -- Jumperl2ess configuration with EEPROM -- Jumper configuration with EEPROM storing Ethernet Address * Direct drive to 4 status LED indicators: transmit, receive, collision, and Thin select -- Transmit LED for packet transmitting status and power indicator -- Receive LED for packet receiving status and Link status -- Collision LED for collision status -- Thin select LED for Thin 10Base-2 port select * ISA NE2000 compatible mode, register compatible to National Semiconductor DP83905 & DP83906 * Optional Full duplex operation with speed up to 20Mbps * Early receive interrupt allows parallel processing of data during receiving * Early transmit correction ability allows parallel processing of data during transmission * Support 16K, 32K Bootrom size * Support PCI 32-bit data path transfaer with enhance 32-bit driver * Software controllable power down feature * Single +5V supply, 0.8um standard CMOS technology * 100 pin PQFP package Buffer RAM Boot ROM Config. EEPROM M-Bus Arbitrator Data Bus FIFO for Remote DMA Remote DMA Registers State Machine & Local DMA Registers & State Machine & Buffer Mgmt. PCI CFG Configuration Registers & EEPROM Control Shadow Ethernet Address PROM Page 1 Registers & Tally Counters MAC Receiver Protocol State Machine & Registers Protocol State Machine & Registers MAC Xmitter PLL & EnDec TP MAU Interface AUI LED & Testing MA0-14 MD0-7 _MSRD, _MSWR, EECS RD+,RD- TD+,TD- RX+,RX- TX+,TX- CI+,CI- THIN MA0 - MA14 MD0 - MD7 Rcv. Data Xmt Data Internal Bus _RXLED, _TXLED, _COLED PCI Bus AD[31:0] PCICLK PCIRST# INTA# CBE#[3:0] IDSEL FRAME# IRDY# TRDY# DEVSEL# STOP# PAR Interface Unit Figure 1: Block Diagram |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |