VT86C926 datasheet(5/24 Pages) ETC

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VIA TECHNOLOGIES, INC.PRELIMINARY VT86C926

PIN DESCRIPTIONS

No.

Name

Type

Description

PCI Bus Interface

98-100, 1-

5, 8-13,

16-17,

26-33,

35-40,

43,44

AD31-0

I/O

Address/Data are multiplexed on the same PCI pins. A bus transaction

consists of an address phase followed by one or more data phases. The

address phase is the clock cycle in which FRAME# is asserted. Write

data is stable and valid when IRDYB is asserted and read data is stable

and valid when TRDYB is asserted.

PCICLK

PCICLK provides timing for all transactions on PCI and is an input pin

to every PCI device.

INTA#

INTA# is an asynchronous signal which is used to request an interrupt

PCIRST#

When PCIRST# is asserted low, the VT86C926 chip performs an

internal system hardware reset. PCIRST# may be asynchronous to CLK

when asserted or deasserted. It is recommended that the deassertion be

synchronous to guarantee clean and bounce free edge.

6, 18, 25,

CBE#[3:0]

Bus Command/Byte Enables are multiplexed on the same PCI pins.

During the address phase of a transaction, CBE3-0B define the Bus

Command. Buring the data phase, CBE3-0B are used as Byte Enables.

The Byte Enables define which physical byte lanes carry meaningful

data. CBE0B applies to byte 0 and CBE3B applies to byte 3.

IDSEL

Used as a chip select during PCI configuration cycle.

FRAME#

Cycle Frame is driven by the current master to indicate the beginning

and duration of an access.

FRAME# is asserted to indicate a bus

transaction is beginning.

While FRAME# is asserted, data transfers

continue. When FRAME# is deasserted, the transaction is in the final

data phase.

IRDY#

Initiator Ready indicates the initiating agent's ability to complete the

current data phase of the transaction. IRDY# is used in conjunction with

TRDY#. A data phase is completed on any clock when both IRDY# and

TRDY# are asserted. During a write, IRDY# indicates that valid data is

present on AD31-0. During a read, it indicates the master is prepared to

accept data. Wait cycles are inserted until both IRDY# and TRDY# are

asserted simultaneously.

TRDY

I/O

Target Ready indicates the target's agent's ability to complete the current

data phase of the transaction.

TRDY# is used in conjunction with

IRDY#. A data phase is completed on any clock when both IRDY# and

TRDY# are asserted. During a read, TRDY# indicates that valid data is

present on AD31-0. During a write, it indicates the target is prepared to

accept data. Wait cycles are inserted until both IRDY# and TRDY# are

asserted simultaneously.

DEVSEL#

I/O

Device Select, when actively driven, indicates the driving device has

decoded its address as the target of the current access. As an input,

DEVSEL# indicates whether any device on the bus has been selected.

STOP#

I/O

VT86C926 drives STOP# to disconnect further traction.

PAR

T/S

Parity is even parity across AD31-0 and CBE3-0B. PARis stable and

valid one clock after the address phase. For data phaases PAR is stable

and valid one clock after either IRDY# is asserted on a write transaction

or TRDY# is asserted on a read transaction.

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