VT86C926 datasheet(7/24 Pages) ETC

7 / 24 page

VIA TECHNOLOGIES, INC.PRELIMINARY VT86C926

External Memory Support

75-72,

67-58,

MA0-MA13,

MA14

Memory Support Address Bus: When RESET is inactive these pins

drive the memory support address bus. These 15 address lines cover up

to 16K bytes memory space. When RESET is active these pins are used

for jumper setting. There are 100K pull-down device on pins.

52-45

MD0-MD7

I/O

Memory Support Data Bus: When RESET is inactive these pins can be

used to access external memory. When RESET is active pin MD3 to

MD7 are used for jumper setting. There are 100K pull-down device on

pins. MD0 to MD2 are used for EEPROM programming interface.

MSRD#

Memory Support Bus Read: Strobes data from external RAM into

VT86C926 controller via the memory support data bus. (Note 1)

Note 1: The Chip Select of external buffer RAM is always enabled.

MSWR#

Memory Support Bus Write: Strobes data from VT86C926 controller

into the external RAM via the memory support data bus. A 100K pull-

down device is connected.

BPCS#

Boot PROM Chip Select: Select the Boot ROM on the memory support

data bus. The ROM address bus is connected to SA bus directly.

EECS

EEPROM Chip Select: Chip select signal for the external EEPROM

when a EEPROM is used to provide the configuration data and

Ethernet Address. A 100K pull-up resistor is connected.

Power Supply & Ground

14, 42, 93,

VDD, VDDIF,

VDD

Positive 5V Supply: Supply power to Internal digital logic, Digital I/O

pads, and TD, TX pads. Double bonding may be required.

15, 41, 94,

VSS, VSSIF,

VSS

Negative Supply: digital ground. Multiple bonding pads are required to

separate core and I/O pads ground.

VDDA

Analog 5V Supply: Supply power to Analog circuit and RX, CI, RD

pads. Seperate power plane may be required.

VSSA

Negative Supply: Analog ground. Sepearte ground plane may be

required.

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