LO

CIT

M

VITESSE

SEMICONDUCTOR CORPORATION

VSC7123

10-Bit Transceiver for Fibre

Channel and Gigabit Ethernet

Data Sheet

G52212-0, Rev 4.3

Page 13

03/25//01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Package Pin Descriptions

Figure 9: Pin Diagram

Table 5: Pin Identifications

Pin #

Name

Description

2,3,4,6

7,8,9,11

12,13

T0,T1,T2,T3

T4,T5,T6,T7

T8,T9

INPUTS - TTL:

10-bit transmit character. Parallel data on this bus is clocked in on the rising edge of

REFCLK. The data bit corresponding to T0 is transmitted first.

22

REFCLK

INPUT - TTL:

This rising edge of this clock latches T(0:9) into the input register. It also provides the

reference clock, at one tenth the baud rate to the PLL.

T5

T4

T7

T8

T9

R6

R5

COMDET

R4

R7

R8

T2

T3

R2

TDI

T6

CAP0

R9

R3

R1

R0

T1

T0

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

63

61

59

57

55

53

51

49

33

35

37

39

41

43

45

47

(Top View)

VSC7123