AS4C4M16SA datasheet(8/54 Pages) ALSC

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AS4C4M16SA - Automotive

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Rev. 1.0-63nm Mar. /2014

CLK

COMMAND

READ A

NOP

CAS# Latency=2

tCK2, DQ

CAS# Latency=3

tCK3, DQ

DOUT A0

DOUT A1

DOUT A2

DOUT A3

DOUT A0

DOUT A1

DOUT A2

DOUT A3

Figure 4. Burst Read Operation (Burst Length = 4, CAS# Latency = 2, 3)

The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e. DQM

latency is two clocks for output buffers). A read burst without the auto precharge function may be

interrupted by a subsequent Read or Write command to the same bank or the other active bank before

the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the

same bank too. The interrupt coming from the Read command can occur on any clock cycle following a

previous Read command (refer to the following figure).

CLK

COMMAND

READ A

READ B

NOP

CAS# Latency=2

tCK2, DQ

CAS# Latency=3

tCK3, DQ

DOUT A0

DOUT B0

DOUT B1

DOUT B2

DOUT A0

DOUT B0

DOUT B1

DOUT B2

DOUT B3

Figure 5. Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)

The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write

command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write command to

suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with

high-impedance on the DQ pins must occur between the last read data and the Write command (refer to

the following three figures). If the data output of the burst read occurs at the second clock of the burst

write, the DQMs must be asserted (HIGH) at least one clock prior to the Write command to avoid internal

bus contention.

CLK

COMMAND

NOP

Bank A

Activate

NOP

READ A

WRITE A

NOP

CAS# Latency=2

tCK2, DQ

DQM

NOP

DIN A0

DIN A1

DIN A2

DIN A3

Figure 6. Read to Write Interval (Burst Length  4, CAS# Latency = 2)

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