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P89C669 Datasheet(PDF) 21 Page - NXP Semiconductors

Part # P89C669
Description  80C51 8-bit microcontroller family with extended memory 96 kB Flash with 2 kB RAM
PDF  33 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

P89C669 Datasheet(HTML) 21 Page - NXP Semiconductors

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Philips Semiconductors
P89C669
80C51 8-bit microcontroller family with extended memory
Product data
Rev. 02 — 13 November 2003
21 of 33
9397 750 12299
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
[3]
Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.
[4]
Parts are tested down to 2 MHz, but are guaranteed to operate down to 0 Hz.
10.1 Explanation of AC symbols
Each timing symbol has five characters. The first character is always ‘t’ ( = time). The
other characters, depending on their positions, indicate the name of a signal or the
logical status of that signal. The designations are:
A — Address
C — Clock
D — Input data
H — Logic level HIGH
I — Instruction (program memory contents)
L — Logic level LOW, or ALE
P — PSEN
Q — Output data
R — RD signal
t — Time
V — Valid
W — WR signal
X — No longer a valid logic level
Z — Float
Table 10:
I2C-bus interface characteristics
Symbol
Parameter
Conditions
Input
Output
tHD;STA
START condition hold time
≥ 7t
CLCL
> 4.0
µs
tLOW
SCL LOW time
≥ 8t
CLCL
> 4.7
µs
tHIGH
SCL HIGH time
≥ 7t
CLCL
> 4.0
µs
tRC
SCL rise time
≤ 1 µs-
tFC
SCL fall time
≤ 0.3 µs
< 0.3
µs
tSU;DAT1
Data set-up time
≥ 250 ns
> 10tCLCL − tRD
tSU;DAT2
SDA set-up time
before repeated START
condition
≥ 250 ns
> 1
µs
tSU;DAT3
SDA set-up time
before STOP condition
≥ 250 ns
> 4tCLCL
tHD;DAT
Data hold time
≥ 0ns
> 4tCLCL - tFC
tSU;STA
Repeated START set-up
time
≥ 7t
CLCL
> 4.7
µs
tSU;STO
STOP condition set-up time
≥ 7tCLCL
> 4.0
µs
tBUF
Bus free time
≥ 7tCLCL
> 4.7
µs
tRD
SDA rise time
≤ 1 µs-
tFD
SDA fall time
≤ 300 ns
< 0.3
µs



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