ADT7476AARQZ-R datasheet(52/69 Pages) ONSEMI

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ADT7476A

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Table 49. ADT7476A REGISTERS (continued)

Addr

Lock-

able

De-

fault

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Desc

R/W

0x7A

R/W

THERM Timer

Limit

LIMT

0x00

−

0x7B

R/W

TACH Pulses

per Revolution

FAN4

FAN3

FAN2

FAN1

0x55

−

0x7C

R/W

Configuration

THERM

Local

THERM

VID/

GPIO

GPIO6P

GPIO6D

Temp

Offset

2sC

0x01

Yes

0x7D

R/W

Configuration

BpAtt

12 V

BpAtt

5.0 V

BpAtt

VCCP

BpAtt

2.5 V

Max

Speed

THERM

Disable

PIN14

FUNC

PIN14

FUNC

0x00

Yes

0x7E

Test 1

DO NOT WRITE TO THESE REGISTERS

0x00

Yes

0x7F

Test 2

DO NOT WRITE TO THESE REGISTERS

0x00

Yes

Table 50. REGISTER 0x10 − CONFIGURATION REGISTER 6 (POWER-ON DEFAULT = 0x00) (Note 1 and 2)

Bit No.

Mnemonic

R/W

Description

[0]

SlowFan

Remote 1

R/W

When this bit is set, Fan 1 smoothing times are multiplied x4 for Remote 1 temperature

channel (as defined in Register 0x62).

[1]

SlowFan

Local

R/W

When this bit is set, Fan 2 smoothing times are multiplied x4 for local temperature channel

(as defined in Register 0x63).

[2]

SlowFan

Remote 2

R/W

When this bit is set, Fan 3 smoothing times are multiplied x4 for Remote 2 temperature

channel (as defined in Register 0x63).

[3]

THERM in

Manual

R/W

When this bit is set, THERM is enabled in manual mode. (Note 1)

[4]

SlaveEn

R/W

Setting this bit configures the ADT7476A as a slave for use in fan sync mode.

[5]

MasterEn

R/W

Setting this bit configures the ADT7476A as a master for use in fan sync mode.

[6]

VCCP Low

R/W

VCCPLow = 1. When the power is supplied from 3.3 V STANDBY and the core voltage (VCCP)

drops below its VCCP low limit value (Register 0x46), the following occurs:

Status Bit 1 in Interrupt Status Register 1 is set.

SMBALERT is generated, if enabled.

PROCHOT monitoring is disabled.

Everything is re-enabled once VCCP increases above the VCCP low limit.When VCCP increases

above the low limit:

PROCHOT monitoring is enabled.

Fans return to their programmed state after a spin-up cycle.

[7]

ExtraSlow

R/W

When this bit is set, all fan smoothing times are increased by a further 39.2%

1. A THERM event always overrides any fan setting (even when fans are disabled).

2. This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to this register fail.

Table 51. REGISTER 0x11 − CONFIGURATION REGISTER 7 (POWER-ON DEFAULT = 0x00) (Note 1)

Bit No.

Mnemonic

R/W

Description

[0]

DisTHERM

Hys

Read/Write

Setting This Bit to 1 Disables THERM Hysteresis

[7:1]

Reserved

N/A

Reserved. Do Not Write to These Bits

1. This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to this register fail.

ADT7476AARQZ-R Datasheet(PDF) 52 Page - ON Semiconductor

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