ADT7476AARQZ-R datasheet(23/69 Pages) ONSEMI

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ADT7476A

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Note that:

• The SMBALERT output remains low for the entire

duration that a reading is out-of-limit and until the

status register has been read. This has implications on

how software handles the interrupt.

• THERM overtemperature events are not sticky. They

reset immediately after the overtemperature condition

ceases.

Handling SMBALERT Interrupts

To prevent the system from being tied up servicing

interrupts, it is recommend to handle the SMBALERT

interrupt as follows:

1. Detect the SMBALERT assertion.

2. Enter the interrupt handler.

3. Read the status registers to identify the interrupt

source.

4. Mask the interrupt source by setting the

appropriate mask bit in the interrupt mask registers

(0x74 and 0x75).

5. Take the appropriate action for a given interrupt

source.

6. Exit the interrupt handler.

7. Periodically poll the status registers. If the

interrupt status bit has cleared, reset the

corresponding interrupt mask bit to 0. This causes

the SMBALERT output and status bits to behave

as shown in Figure 30.

Figure 30. How Masking the Interrupt Source Affects

SMBALERT Output

HIGH LIMIT

TEMPERATURE

“STICKY”

STATUS BIT

SMBALERT

CLEARED ON READ

(TEMP BELOW LIMIT)

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

INTERRUPT

MASK BIT SET

INTERRUPT MASK BIT

CLEARED

(SMBALERT RE-ARMED)

Masking Interrupt Sources

Interrupt Mask Register 1 (0x74) and Interrupt Mask

masked to prevent SMBALERT interrupts.

NOTE: Masking an interrupt source prevents only the SMBALERT

output from being asserted; the appropriate status bit is set

normally.

ADT7476AARQZ-R Datasheet(PDF) 23 Page - ON Semiconductor

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