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7032STC Datasheet(PDF) 39 Page - Altera Corporation

Part # 7032STC
Description  Programmable Logic Device Family
PDF  66 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

7032STC Datasheet(HTML) 39 Page - Altera Corporation

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Altera Corporation
39
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2)
This parameter applies to MAX 7000E devices only.
(3)
This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter
must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal
path.
(4)
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(5)
These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(6)
The fMAX values represent the highest frequency for pipelined data.
(7)
Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use.
(8)
The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells
running in the low-power mode.
Tables 27 and 28 show the EPM7032S AC operating conditions.
Table 27. EPM7032S External Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-6
-7
-10
Min
Max
Min
Max
Min
Max
Min
Max
tPD1
Input to non-registered output
C1 = 35 pF
5.0
6.0
7.5
10.0
ns
tPD2
I/O input to non-registered
output
C1 = 35 pF
5.0
6.0
7.5
10.0
ns
tSU
Global clock setup time
2.9
4.0
5.0
7.0
ns
tH
Global clock hold time
0.0
0.0
0.0
0.0
ns
tFSU
Global clock setup time of fast
input
2.5
2.5
2.5
3.0
ns
tFH
Global clock hold time of fast
input
0.0
0.0
0.0
0.5
ns
tCO1
Global clock to output delay
C1 = 35 pF
3.2
3.5
4.3
5.0
ns
tCH
Global clock high time
2.0
2.5
3.0
4.0
ns
tCL
Global clock low time
2.0
2.5
3.0
4.0
ns
tASU
Array clock setup time
0.7
0.9
1.1
2.0
ns
tAH
Array clock hold time
1.8
2.1
2.7
3.0
ns
tACO1
Array clock to output delay
C1 = 35 pF
5.4
6.6
8.2
10.0
ns
tACH
Array clock high time
2.5
2.5
3.0
4.0
ns
tACL
Array clock low time
2.5
2.5
3.0
4.0
ns
tCPPW
Minimum pulse width for clear
and preset
(2)
2.5
2.5
3.0
4.0
ns
tODH
Output data hold time after
clock
C1 = 35 pF (3)
1.0
1.0
1.0
1.0
ns
tCNT
Minimum global clock period
5.7
7.0
8.6
10.0
ns
fCNT
Maximum internal global clock
frequency
(4)
175.4
142.9
116.3
100.0
MHz
tACNT
Minimum array clock period
5.7
7.0
8.6
10.0
ns



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