7032STC datasheet(41/66 Pages) ALTERA

41 / 66 page

Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Notes to tables:

(1)

These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more

information on switching waveforms.

(2)

This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter

must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal

path.

(3)

This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This

parameter applies for both global and array clocking.

(4)

These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.

(5)

The fMAX values represent the highest frequency for pipelined data.

(6)

Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use.

(7)

For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,

these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these

devices, add an additional 0.1 ns to the PIA timing value.

(8)

The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells

running in the low-power mode.

Tables 29 and 30 show the EPM7064S AC operating conditions.

tPIA

PIA delay

(7)

1.1

1.4

1.0

tLPA

Low-power adder

(8)

12.0

10.0

11.0

Table 28. EPM7032S Internal Timing Parameters

Note (1)

Symbol

Parameter

Conditions

Speed Grade

Unit

-5

-6

-7

-10

Min

Max

Min

Max

Min

Max

Min

Max

Table 29. EPM7064S External Timing Parameters (Part 1 of 2)

Note (1)

Symbol

Parameter

Conditions

Speed Grade

Unit

-5

-6

-7

-10

MinMax MinMax MinMax MinMax

tPD1

Input to non-registered output

C1 = 35 pF

5.0

6.0

7.5

10.0

tPD2

I/O input to non-registered

output

C1 = 35 pF

5.0

6.0

7.5

10.0

tSU

Global clock setup time

2.9

3.6

6.0

7.0

Global clock hold time

0.0

tFSU

Global clock setup time of fast

input

2.5

3.0

tFH

Global clock hold time of fast

input

0.0

0.5

tCO1

Global clock to output delay

C1 = 35 pF

3.2

4.0

4.5

5.0

tCH

Global clock high time

2.0

2.5

3.0

4.0

tCL

Global clock low time

2.0

2.5

3.0

4.0

tASU

Array clock setup time

0.7

0.9

3.0

2.0

tAH

Array clock hold time

1.8

2.1

2.0

3.0

7032STC Datasheet(PDF) 41 Page - Altera Corporation

7032STC Datasheet(HTML) 41 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL