MAX6440UTF datasheet(4/14 Pages) MAXIM

4 / 14 page

Low-Power, Single-/Dual-Level Battery Monitors

with Hysteresis and Integrated µP Reset

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VBATT = 1.2V to 5.5V, VCC = 1.2V to 5.5V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

LBO, LBOL, LBOH, LBOLH

Timeout Period

tLBOP

VBATT rising above threshold

150

225

300

LBO, LBOL, LBOH, LBOLH

Delay Time

tLBOD

VBATT falling below threshold

100

µs

(VBATT or VCC)

≥ 1.2V, ISINK = 50µA,

asserted low

0.3

(VBATT or VCC)

≥ 1.6V, ISINK = 100µA,

asserted low

0.3

(VBATT or VCC)

≥ 2.7V, ISINK = 1.2mA,

asserted low

0.3

LBO, LBOL, LBOH, LBOLH

Output Low

(Open Drain)

VOL

(VBATT or VCC)

≥ 4.5V, ISINK = 3.2mA,

asserted low

0.3

LBO, LBOL, LBOH, LBOLH

Output Open-Drain Leakage

Current

ILKG

Output deasserted

500

MAX64_ _ _ _ _ _ T

3.000

3.075

3.150

MAX64_ _ _ _ _ _ S

2.850

2.925

3.000

MAX64_ _ _ _ _ _ R

2.550

2.625

2.700

MAX64_ _ _ _ _ _ Z

2.250

2.313

2.375

MAX64_ _ _ _ _ _ Y

2.125

2.188

2.250

MAX64_ _ _ _ _ _ W

1.620

1.665

1.710

VCC Reset Threshold

VTH

MAX64_ _ _ _ _ _ V

1.530

1.575

1.620

VCC Reset Hysteresis

0.3

VCC to RESET Delay

VCC falling at 10mV/µs from (VTH + 100mV)

to (VTH - 100mV)

µs

MAX64_ _ _ _ _ _ _ D3

150

225

300

VCC to RESET Timeout Period

tRP

MAX64_ _ _ _ _ _ _ D7

1200

1800

2400

VIL

0.3 x VCC

MR Input Voltage

VIH

0.7 x VCC

MR Minimum Pulse Width

tMPW

1µs

MR Glitch Rejection

100

MR to RESET Delay

200

MR Reset Timeout Period

tMRP

150

225

300

MR Pullup Resistance

MR to VCC

750

1500

2250

Ω

MR Rising Debounce Period

tDEB

(Note 3)

150

225

300

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