MAX6440UTF datasheet(5/14 Pages) MAXIM

5 / 14 page

Low-Power, Single-/Dual-Level Battery Monitors

with Hysteresis and Integrated µP Reset

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VBATT = 1.2V to 5.5V, VCC = 1.2V to 5.5V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

VCC

≥ 1.53V, ISOURCE = 100µA, RESET

deasserted

0.8 x VCC

RESET Output High

(Push-Pull)

VOH

VCC

≥ 2.55V, ISOURCE = 500µA, RESET

deasserted

0.8 x VCC

VCC

≥ 1.0V, ISINK = 50µA, RESET asserted

0.3

VCC

≥ 1.2V, ISINK = 100µA, RESET asserted

0.3

RESET Output Low

VOL

VCC

≥ 2.12V, ISINK = 1.2mA, RESET

asserted

0.3

RESET Output Leakage Current

(Open Drain)

RESET deasserted

500

Typical Operating Characteristics

(VBATT = 1.2V to 5.5V, VCC = 1.2V to 5.5V, unless otherwise specified. Typical values are at TA = +25°C.)

SUPPLY CURRENT vs. TEMPERATURE

VCC = 3.3V, VBATT = 3.6V

TEMPERATURE (

°C)

TOTAL

IBATT

-20

-40

ICC

NORMALIZED LBO TIMEOUT PERIOD

vs. TEMPERATURE

TEMPERATURE (

°C)

-20

0.95

1.00

1.05

1.10

0.90

-40

NORMALIZED RESET TIMEOUT PERIOD

vs. TEMPERATURE

TEMPERATURE (

°C)

-20

0.990

0.985

1.000

0.995

1.005

1.010

1.015

0.980

-40

Note 1: Production testing done at TA = +25°C; limits over temperature guaranteed by design only.

Note 2: The device is powered up by the highest voltage between VBATT and VCC.

Note 3: MR input ignores falling input pulses, which occur within the MR debounce period (tDEB) after a valid MR reset assertion.

This prevents invalid reset assertion due to switch bounce.

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