MIC2111B datasheet(29/35 Pages) MICREL

29 / 35 page

Micrel, Inc.

MIC2111B

October 13, 2015

Revision 2.1

Design and Layout Checklist

•

Ceramic capacitor placed between the VIN and PGND

close to power module input.

•

Output ceramic capacitors should be placed next to

inductor output node for high-frequency decoupling.

•

The signal and power ground planes must be

separated to prevent high current and fast switching

signals from interfering with the low level, noise

sensitive analog signals. These planes should be

connected at only 1 point.

•

The following signals and their components should be

decoupled or referenced to the power ground plane:

−

VIN, VCC, PGND

•

These

analog

signals

should

referenced

decoupled to the analog ground plane:

−

VCC, SS, PG, COMP, FB, VOUT, and AGND

•

Place the current-sense lines in differential way. The

trace coming from the switch node to this resistor has

high dv/dt and should be routed away from other noise

sensitive components and traces.

•

The remote sense traces must be routed close

together or on adjacent layers to minimize noise

pickup. The traces should be routed away from the

switch node, inductors, and other high dv/dt or di/dt

sources.

MIC2111B Datasheet(PDF) 29 Page - Micrel Semiconductor

MIC2111B Datasheet(HTML) 29 Page - Micrel Semiconductor

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