VDP3133Y datasheet(43/76 Pages) MICRONAS

43 / 76 page

ADVANCE INFORMATION

VDP 313xY

Micronas

luma/chroma delay adjust. The setting is updated when ’sdt’ reg-

ister is updated.

bit[5:0]

reserved, set to zero

bit[11:6]

luma delay in clocks,

allowed range is +1...

−7

0LDLY

Input select:

writing to this register will also initialize the

standard

bit[1:0]

luma selector

VIN1

VIN2

VIN3

VIN4

bit[2]

chroma selector

0CIN1

1CIN2

bit[4:3]

IF compensation

off

6 dB/Okt

12 dB/Okt

10 dB/MHz only for SECAM

bit[6:5]

chroma bandwidth selector

narrow

normal

broad

wide

bit[7]

0/1

adaptive/fixed SECAM notch filter

bit[8]

0/1

enable luma lowpass filter

bit[10:9]

hpll speed

no change

terrestrial

vcr

mixed

bit[11]

status bit, write 0, this bit is set to 1 to indicate

operation complete.

INSEL

VIS

CIS

IFC

CBW

FNTCH

LOWP

HPLLMD

Table 2–6: Control Registers of the Fast Processor for control of the video frontend functions

−default values are initializied at reset

FP Sub-

address

Function

Default

Name

(hex)

VDP3133Y Datasheet(PDF) 43 Page - Micronas

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