GL603USB-A datasheet(12/41 Pages) ETC

12 / 41 page

09/22/00

GL603USB/GL603USB-A/GL603USB-B

Revision 1.4

FUNCTIONAL DESCRIPTION

The Genesys Logic GL603USB micro-controller is optimized for USB & PS/2 combo 2D/3D/4D mouse.

This USB microcontroller conforms to the low-speed (1.5Mbps) requirements of the USB Specification

version 1.1. The micro-controller is a self-contained unit with an USB SIE, an USB transceiver, an 8-bits

RISC-like microcontroller, a timer, data and program memories. It supports one USB device address and

two endpoints (include endpoint 0). The USB transceiver can be disabled in PS/2 mode and D+/D- can be

used as PS/2 CLK and DATA.

4.1

MEMORY ORGANIZATION

The memory in the microcontroller is organized into user program memory in program ROM and data

memory in SRAM space.

4.1.1

Program Memory Organization

The 12-bit Program Counter (PC) is capable of addressing 4K x 14 of program space. However, the

program space of the GL603USB is 2.75K x 14. The program memory space is divided into two functional

groups: Interrupt Vectors and program code. After a reset, the Program Counter points to location zero of

the program space. After a timer interrupt, the Program Counter points the location 0x0004 of the program

space.

After Reset

→

Address

0x0000

Reset Vector

After Timer Interrupt

→

0x0004

Timer Interrupt Vector

0x0005

0x0AFF

2.75K x 14 ROM

Figure 4-1 Program Memory Space

4.1.2

Data Memory Organization

The data memory is partitioned into two banks that contain the General Purpose Registers, MCU Function

Registers and USB Function Registers. Bit BS is the bank select bit.

BS (STATUS<5>) = 1

→ Bank 1

BS (STATUS<5>) = 0

→ Bank 0

The lower locations of each Bank are reserved for MCU Function Registers and USB Function Registers.

Above the MCU Function Registers and USB Function Registers are General Purpose Registers

implemented as SRAM. Both Bank 0 and Bank 1 contain MCU Function Registers. USB Function

Registers are located in Bank 0. Some “high use” MCU Function Registers from Bank 0 are mirrored in

Bank 1 for code reduction and quicker access.

Data Memory

Address

Data Memory

Address

00h

INDR

80h

INDR

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