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DM9102AT Datasheet(PDF) 26 Page - List of Unclassifed Manufacturers

Part # DM9102AT
Description  Single Chip Fast Ethernet NIC controller
PDF  77 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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DM9102AT Datasheet(HTML) 26 Page - List of Unclassifed Manufacturers

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DM9102A
Single Chip Fast Ethernet NIC controller
26
Final
Version: DM9102A-DS-F03
August 28, 2000
1. System Control Register (CR0)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
987
6
54
3
2
1
0
Bit
Name
Default
Description
24:22
Reserved
0,RO
Reserved
21
MRM
0,RW
Memory Read Multiple
When set, the DM9102A will use memory read multiple command (C/BE3~0 =
1100) when it initialize the memory read burst transaction as a master device.
When reset, it will use memory read command (C/BE3 ~ 0 = 0110) for the same
master operation.
20
Reserved
0,RO
Reserved
19:17
TXAP
000,RW
Transmit Automatic polling interval time
When set, the DM9102A will poll transmit descriptor automatically when it is in the
suspend state due to buffer unavailable. The polling interval time is programmable
based on the table shown below.
Bit 19
Bit 18
Bit 17
Time Interval
0
0
0
No polling
0
0
1
200us
0
1
0
800us
0
1
1
1.6ms
1
0
0
12.8us
1
0
1
25.6us
1
1
0
51.2us
1
1
1
102.4us
16
Reserved
0,RO
Reserved
15:14
ABA
00,RW
Address Boundary Alignment
When set, the DM9102A will execute each burst cycles to stop at the programmed
address boundary. The address boundary can be programmed to be 8, 16, or 32
doubleword as shown below.
Bit 15 Bit 14
Alignment Boundary
0
0
Reserved
0
1
8-double word
1
0
16-double word
1
1
32-double word
13:8
BL
000000,
RW
Burst Length
When reset, the DM9102A’s burst length in one DMA transfer is limited by the
amount of data in the receive FIFO ( when receive ) or the amount of free space in
the transmit FIFO (when transmit ). When set, the DMA’s burst length is limited by
the programmed value. The permissible values are 0, 1, 2, 4, 8, 16, or 32
doublewords.
7
Reserved
0,RO
Reserved
6:2
Reserved
00000
1
Reserved
0,RO
Reserved



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