DM9102AT datasheet(58/77 Pages) ETC

58 / 77 page

DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

Power Management

1. Overview

The DM9102A supports power management mechanism. It

complies with the ACPI Specification Rev 1.0, the Network

Device Class Power Management Specification Rev 1.0,

and PCI Bus Power Management Interface Specification

Rev 1.0. In addition, it also support Wake-On LAN (WOL)

which is the features of the AMD’s Magic Packet™

technology. With this function, it can wake-up a remote

sleeping station.

2. PCI Function Power Management States

The DM9102A supports PCI function power states D0,

D3(hot), D3(cold), and not supports D1, D2 states.

Additional PCI signal PME# (power management event,

open drain) to pin A19 of the standard PCI connector.

D0: normal & fully functional state

D3(hot) : For controller, configuration space can be

accessed and wake-up on LAN circuit can be enabled.

PME# operational circuit is active, full function is supported

to detect the wake-up Frame & Link status. Because of

functions in D3(hot) must respond to configuration space

accesses as long as power and clock are supplied so that

they can be returned to D0 state by software.

D3(cold) : If Vcc is removed from a PCI device, all of its PCI

functions transition immediately to D3(cold), no bus

transaction is active under no pci_clk condition and wake-up

on LAN operation should be alive. PME# operational circuit

is active. Full function is supported under auxiliary power to

detect the wake-up Frame & Link status. When power

restored, PCI RST# must be asserted and functions will

return to D0 with a full PCI Spec. 2.2 compliant power-on

reset sequence. The power required in D3(cold) must be

provided by some auxiliary power source.

3. The Power Management Operation

It complies with the PCI Bus Power Management Interface

Specification Rev. 1.0. The Power ManagementEvent

(PME#) signal is an optional open drain, active low signal

that is intended to be driven low by a PCI function to request

a change in its current power management state and/or to

indicate that a power management event has occurred.

The PME# signal has been assigned to pin A19 of the

standard PCI Connector configuration. The assertion and

de-assertion of PME# is asynchronous to the PCI clock.

Software will enable its use by setting the PME_En bit in the

PMCSR (write 1 to PMCSR<8>). When a PCI function

generates or detects an event that requires the system to

change its power state, the function will assert PME#. It

must continue to assert PME# until software either clears

the PME_En bit (PMCSR<8> is set to 0) or clears the

PME_Status bit in the PMCSR (write 1 to PMCSR<15>).

DM9102A support three main categories of network device

wake-up events specified in Network Device Class Power

Management Rev1.0. That is, the DM9102A can monitor

the network for a Link Change, Magic Packet or a Wake-up

Frame and notify the system by generating PME# if any of

three events occurs. Program the PCIUSR (offset = 40h)

can select the PME# event, and write 1 to PMCSR<15> will

clear the PME#.

a. Detect Network Link State Change

Any link status change will set the wake-up event.

1. Writes 1 into PMCSR<15>(54h) to clear previous PME#

status

2. Writes 1 into PMCSR<8> to enable PME# function

3. Writes 1 into PCIUSR<29> to enable the link status

change function

b. Active Magic Packet Function

Could be optionally enabled from EEPROM contents. Send

a setup frame with a magic node address at first filter

address using perfect address filtering mode.

1. Writes 1 into PMCSR<15> to clear previous PME status

2. Writes 1 into PMCSR<8> to enable PME# function

3. Writes 1 into PCIUSR<27> to enable magic packet

function.

c. Active the Sample Frame Function

Could be optionally enabled from PCIUSR<28>. Sample

frame data and corresponding byte mask are loaded into

transmit FIFO & receive FIFO before entering D3(hot). The

software driver has to stop the TX/RX process before setting

the sample frame and byte mask into the FIFO. Transmit &

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