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DM9161 Datasheet(PDF) 37 Page - List of Unclassifed Manufacturers

Part # DM9161
Description  10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
PDF  47 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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DM9161 Datasheet(HTML) 37 Page - List of Unclassifed Manufacturers

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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final
37
Version: DM9161-DS-F02
May 10,2002
9.4.12 MII 10BASE-T Receive Nibble Timing Parameters
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
tRXs
RXD [0:3), RXDV, RXER Setup To RXCLK High
5
---
---
ns
tRXh
RXD [0:3], RXDV, RXER Hold From RXCLK High
5
---
---
ns
tRXpd
RXI In To RXD [0:3] Out (Rx Latency)
---
7
---
BT
t1
CRS Asserted To RXD [0:3], RXDV, RXER
1
14
20
BT
t2
CRS De-asserted To RXD [0:3], RXDV, RXER
---
---
3
BT
t3
RXI In To CRS Asserted
1
2
4
BT
t4
RXI Quiet To CRS De-asserted
1
10
15
BT
9.4.13 MII 10BASE-T Receive Nibble Timing Diagram
RXCLK
t2
t1
tTX
pd
RXD [0:3],
RXDV, RXER
CRS
RX+/-
tRX
S
tRX
h
t4
t3
9.4.14 Auto-negotiation and Fast Link Pulse Timing Parameters
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
t1
Clock/Data Pulse Width
---
100
---
ns
t2
Clock Pulse To Data Pulse Period
55.5
62.5
69.5
us
DATA = 1
t3
Clock Pulse To Clock Pulse Period
111
125
139
us
t4
FLP Burst Width
-
2
-
ms
t5
FLP Burst To FLP Burst Period
8
24
ms
-
Clock/Data Pulses in a Burst
17
33
pulse
9.4.15 Auto-negotiation and Fast Link Pulse Timing Diagram



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