TAS5001

SLES009A – SEPTEMBER 2001 – REVISED DECEMBER 2001

14

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PARAMETER MEASUREMENT INFORMATION

th(SDIN)

tsu(SDIN)

SCLK

SDIN

Figure 11. Right-Justified, IIS, Left-Justified Serial Protocol Timing

tsu(LRCLK)

SCLK

LRCLK

NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns)

Figure 12. Right, Left, and IIS Serial Mode Timing Requirement

t(MSD)

t(MLRD)

SCLK

LRCLK

(Output)

MCLK

(Output)

Figure 13. Serial Audio Ports Master Mode Timing

th(SDIN)

tsu(SDIN)

SCLK

LRCLK

SDIN

tsu(LRCLK)

tw(FSHIGH)

th(LRCLK)

Figure 14. DSP Serial Port Timing