important to have good thermal conduction with a proper

layout to reduce thermal resistance.

POWER EFFICIENCY

An ideal power efficiency for a voltage doubler switched

capacitor converter is given as the output voltage of the

doubler over twice the input voltage as follows:

Efficiency = (V

V

In the case of the LM2792, a more accurate efficiency cal-

culation can be applied as the given formula below.

Efficiency = ((V

It is clear that the efficiency will depend on the supply voltage

in the above equation. As such, the lower the supply voltage,

the higher the efficiency.

POWER DISSIPATION

The maximum allowable power dissipation that this package

is capable of handling can be determined as follows:

P

θ

JA

where T

ambient temperature, and

θ

JA

is the junction-to-ambient

thermal resistance of the specified package.

The actual power dissipation of the device can be calculated

using this equation:

P

As an example, if V

= 3.0V and worse case current consumption is 32mA (17mA

for each diode).

P

Power dissipation must be less than that allowed by the

package. Please refer to the Absolute Maximum Rating of

the LM2792.

PCB LAYOUT CONSIDERATIONS

The LLP is a leadframe based Chip Scale Package (CSP)

with very good thermal properties. This package has an

exposed DAP (die attach pad) at the center of the package

measuring 2.0mm x 1.2mm. The main advantage of this

exposed DAP is to offer lower thermal resistance when it is

soldered to the thermal land on the PCB. For PCB layout,

National highly recommends a 1:1 ratio between the pack-

age and the PCB thermal land. To further enhance thermal

conductivity, the PCB thermal land may include vias to a

ground plane. For more detailed instructions on mounting

LLP packages, please refer to National Semiconductor Ap-

plication Note AN-1187.

www.national.com

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