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TMS320DM642GDKA500 Datasheet(PDF) 76 Page - Texas Instruments |
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TMS320DM642GDKA500 Datasheet(HTML) 76 Page - Texas Instruments |
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76 / 178 page  www.ti.com 5.3.5 Power-Down Modes Logic PWRD Internal Clock Tree CPU IFR IER CSR PD1 PD2 Power- Down Logic Clock PLL CLKIN RESET CLKOUT6 PD3 Internal Peripherals CLKOUT4 Clock and Dividers Distribution TMS320DM642 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor SPRS200J – JULY 2002 – REVISED AUGUST 2005 The McASP0, McBSP0, McBSP1, VP0, VP1, VP2, and I2C0 peripheral functions are selected via the peripheral configuration (PERCFG) register bits. For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the Device Configurations section of this document. Figure 5-6 shows the power-down mode logic on the DM642. A. External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic. Figure 5-6. Power-Down Mode Logic(A) 76 DM642 Peripheral Information and Electrical Specifications |
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