| Electronic Components Datasheet Search |
|
LAN9117 Datasheet(PDF) 4 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
LAN9117 Datasheet(HTML) 4 Page - Microchip Technology |
|
4 / 114 page ![]() LAN9117 DS00002267A-page 4 2005-2016 Microchip Technology Inc. 1.0 GENERAL DESCRIPTION The LAN9117 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where per- formance, flexibility, ease of integration and system cost control are required. The LAN9117 has been specifically archi- tected to provide the highest performance possible for any 16-bit application. The LAN9117 is fully IEEE 802.3 10BASE- T and 802.3u 100BASE-TX compliant. The LAN9117 includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit microprocessors and microcontrollers as well as 32-bit microprocessors exposing a 16-bit external bus. The LAN9117 includes large transmit and receive data FIFOs with a high-speed host bus interface to accommodate high bandwidth, high latency applications. In addition, the LAN9117 memory buffer architecture allows the most efficient use of memory resources by optimizing packet granularity. Applications The LAN9117 is well suited for many medium-high-performance embedded applications, including: • Medium-range cable, satellite and IP set-top boxes • High-end audio distribution systems • Digital video recorders • DVD Recorders/Players • High-definition televisions • Digital media clients/servers • Home gateways The LAN9117 also supports features which reduce or eliminate packet loss. Its internal 16-KByte SRAM can hold over 200 received packets. If the receive FIFO gets too full, the LAN9117 can automatically generate flow control packets to the remote node, or assert back-pressure on the remote node by generating network collisions. The LAN9117 supports numerous power management and wakeup features. The LAN9117 can be placed in a reduced power mode and can be programmed to issue an external wake signal via several methods, including “Magic Packet”, “Wake on LAN” and “Link Status Change”. This signal is ideal for triggering system power-up using remote Ethernet wakeup events. The device can be removed from the low power state via a host processor command. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |