LAN9250 datasheet(156/421 Pages) MICROCHIP

156 / 421 page

LAN9250

DS00001913A-page 156

 2015 Microchip Technology Inc.

11.8.1

TX CHECKSUM CALCULATION

The TX checksum calculation is performed using the same operation as the RX checksum shown in Section 11.7.1, with

the exception that the calculation starts as indicated by the TX checksum preamble and the transmitted checksum is

the one’s-compliment of the calculated value.

UDP checksums are optional under IPv4, and a checksum value of zero indicates to the receiver that no checksum was

calculated. Under IPv6, however, according to RFC 2460, the UDP checksum is not optional. A calculated checksum

that yields a result of zero must be changed to FFFFh for insertion into the UDP header. IPv6 receivers discard UDP

packets containing a zero checksum. Bit 31 of the checksum preamble specifies if a result of 0x0000 should be changed

to 0xFFFF. This allows the choice of checksum usage for UDP and other purposes.

11.9

Host MAC Address

The Host MAC address is configured via the Host MAC Address Low Register (HMAC_ADDRL) and Host MAC Address

High Register (HMAC_ADDRH). These registers contain the 48-bit physical address of the Host MAC. The contents of

these registers may be loaded directly by the host, or optionally, by the EEPROM Loader from EEPROM at power-on

(if a programmed EEPROM is detected).

Table 11-9 below illustrates the byte ordering of the HMAC_ADDRL and HMAC_ADDRH registers with respect to the

reception of the Ethernet physical address. Also shown is the correlation between the EEPROM addresses and

HMAC_ADDRL and HMAC_ADDRH registers.

For example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the HMAC_ADDRL and HMAC_ADDRH

registers would be programmed as shown in Figure 11-9. The values required to automatically load this configuration

from the EEPROM are also shown.

Note:

By convention, the right nibble of the left most byte of the Ethernet address (in this example, the 2 of the

12h) is the most significant nibble and is transmitted/received first.

TABLE 11-9:

EEPROM BYTE ORDERING AND REGISTER CORRELATION

EEPROM Address

Order of Reception on Ethernet

01h

HMAC_ADDRL[7:0]

1st

02h

HMAC_ADDRL[15:8]

2nd

03h

HMAC_ADDRL[23:16]

3rd

04h

HMAC_ADDRL[31:24]

4th

05h

HMAC_ADDRH[7:0]

5th

06h

HMAC_ADDRH[15:8]

6th

FIGURE 11-9:

EXAMPLE EEPROM MAC ADDRESS SETUP

12h

34h

56h

78h

9Ah

BCh

A5h

12h

34h

56h

78h

9Ah

BCh

00h

01h

02h

03h

04h

05h

06h

EEPROM

HMAC_ADDRH

HMAC_ADDRL

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