LAN9250 datasheet(178/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 178

 2015 Microchip Technology Inc.

11.14.2

RECEIVE CONFIGURATION REGISTER (RX_CFG)

This register controls the Host MAC receive engine.

Offset:

06Ch

Size:

32 bits

Bits

Description

Type

Default

31:30

RX End Alignment (RX_EA)

This field specifies the alignment that must be maintained on the last data

transfer of a buffer. The device will add extra DWORDs of data up to the

alignment specified in the table below. The host is responsible for removing

these extra DWORDs. This mechanism can be used to maintain cache line

alignment on host processors.

Note:

The desired RX End Alignment must be set before reading a

packet. The RX End Alignment can be changed between reading

receive packets, but must not be changed if the packet is partially

read.

R/W

00b

29:28

RESERVED

27:16

RX DMA Count (RX_DMA_CNT)

This 12-bit field indicates the amount of data, in DWORDs, to be transferred

out of the RX Data FIFO before asserting the RX DMA Interrupt (RXD_INT).

After being set, this field is decremented for each DWORD of data that is

read from the RX Data FIFO. This field can be overwritten with a new value

before it reaches zero.

R/W

000h

Force RX Discard (RX_DUMP)

When a 1 is written to this bit, the RX Data and Status FIFO’s are cleared of

all pending data and the RX data and status pointers are cleared to zero.

Note:

Please refer to Section 11.12.1.2, "Force Receiver Discard

(Receiver Dump)," on page 172 for a detailed description

regarding the use of RX_DUMP.

14:13

RESERVED

Bit

Values

[31:30]

End Alignment

4-Byte Alignment

16-Byte Alignment

32-Byte Alignment

RESERVED

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