LAN9250 datasheet(174/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 174

 2015 Microchip Technology Inc.

11.12.4

STOPPING AND STARTING THE RECEIVER

To stop the receiver, the host must clear the RXEN bit in the Host MAC Control Register (HMAC_CR). When the receiver

is halted, the RXSTOP_INT will be pulsed and reflected in the Interrupt Status Register (INT_STS). Once stopped, the

host can optionally clear the RX Status and RX Data FIFOs. The host must re-enable the receiver by setting the RXEN

bit.

11.12.5

RECEIVER ERRORS

If the Receiver Error (RXE) flag is asserted in the Interrupt Status Register (INT_STS) for any reason, the receiver will

continue operation. RX Error (RXE) will be asserted under the following conditions:

• A host underrun of RX Data FIFO

• A host underrun of the RX Status FIFO

• An overrun of the RX Status FIFO (RX Status FIFO Full Interrupt (RSFF))

It is the duty of the host to identify and resolve any error conditions.

11.13 IEEE 802.3az Energy Efficient Ethernet

The device supports Energy Efficient Ethernet (EEE) in 100 Mbps mode as defined in the most recent version of the

IEEE 802.3az standard.

Energy Efficient Ethernet is enabled via Host MAC Energy Efficient Ethernet (HMAC_EEE_ENABLE) bit in the Host

MAC Control Register (HMAC_CR).

11.13.1

TX LPI GENERATION

The process of when the MAC should indicate LPI requests to the PHY is divided into two sections:

• Client LPI Requests to MAC

• MAC LPI Request to PHY

11.13.1.1

Client LPI Requests to MAC

When the TX FIFO is empty for a time (in us) specified in Host MAC EEE TX LPI Request Delay Register

(HMAC_EEE_TX_LPI_REQ_DELAY) a TX LPI request is asserted to the MAC. A setting of 0 us is possible for this time.

If the TX FIFO becomes not empty while the timer is running, the timer is reset (i.e. empty time is not cumulative). Once

TX LPI is requested and the TX FIFO becomes not empty, the TX LPI request is negated.

The TX FIFO empty timer is reset if Host MAC Energy Efficient Ethernet (HMAC_EEE_ENABLE) in the Host MAC Con-

trol Register (HMAC_CR) is cleared.

TX LPI requests are asserted only if the Host MAC Energy Efficient Ethernet (HMAC_EEE_ENABLE) bit is set, and if

the current speed is 100 Mbps, the current duplex is full (as indicated by the Full Duplex Mode (FDPX) bit of the Host

MAC Control Register (HMAC_CR)) and the auto-negotiation result indicates that both the local and partner device sup-

port EEE 100 Mbps. In order to prevent an unstable link condition, the PHY link status also must indicate “up” for one

second before LPI is requested.

TX LPI requests are asserted even if the Transmitter Enable (TX_ON) bit in the Transmit Configuration Register

(TX_CFG) is cleared.

11.13.1.2

MAC LPI Request to PHY

Lower Power Idle (LPI) is requested by the Host MAC to the PHY using the MII value of TXEN=0, TXER=1,

TXD[3:0]=4’b0001. The MAC always finishes the current packet before signaling TX LPI to the PHY. The MAC will gen-

erate TX LPI requests to the PHY even if the Transmitter Enable (TX_ON) bit in the Transmit Configuration Register

(TX_CFG) is cleared.

802.3az specifies the usage of a simplified full duplex MAC with carrier sense deferral. Basically this means that once

the TX LPI request to the PHY is de-asserted, the Host MAC will defer the time specified in Host MAC EEE Time Wait

TX System Register (HMAC_EEE_TW_TX_SYS) in addition to the normal IPG before sending a frame.

TX LPI COUNTERS

The Host MAC maintains a counter, EEE TX LPI Transitions, that counts the number of times that TX LPI request to the

PHY changes from de-asserted to asserted. The counter is not writable and does not clear on read. The counter is reset

if the Host MAC Energy Efficient Ethernet (HMAC_EEE_ENABLE) bit in the Host MAC Control Register (HMAC_CR) is

low.

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