LAN9250 datasheet(176/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 176

 2015 Microchip Technology Inc.

11.14 Host MAC & FIFO Interface Registers

This section details the directly addressable Host MAC and TX/RX FIFO related System CSRs. These registers allow

for the configuration of the TX/RX FIFO’s, Host MAC and indirect access to the complete set of Host MAC CSRs. The

Host MAC CSRs are accessible through via the Host MAC CSR Interface Command Register (MAC_CSR_CMD) and

Host MAC CSR Interface Data Register (MAC_CSR_DATA).

Note:

For more information on the TX/RX FIFO’s, refer to Section 11.10, "FIFOs".

Note:

The full list of indirectly addressable Host MAC CSRs are described in Section 11.15, "Host MAC Control

and Status Registers," on page 192.

TABLE 11-15: HOST MAC & FIFO INTERFACE LOGIC REGISTERS

Address

068h

FIFO Level Interrupt Register (FIFO_INT)

06Ch

Receive Configuration Register (RX_CFG)

070h

Transmit Configuration Register (TX_CFG)

078h

Receive Datapath Control Register (RX_DP_CTRL)

07Ch

RX FIFO Information Register (RX_FIFO_INF)

080h

TX FIFO Information Register (TX_FIFO_INF)

0A0h

Host MAC RX Dropped Frames Counter Register (RX_DROP)

0A4h

Host MAC CSR Interface Command Register (MAC_CSR_CMD)

0A8h

Host MAC CSR Interface Data Register (MAC_CSR_DATA)

0ACh

Host MAC Automatic Flow Control Configuration Register (AFC_CFG)

0B0h

Host MAC RX LPI Transitions Register (HMAC_RX_LPI_TRANSITION)

0B4h

Host MAC RX LPI Time Register (HMAC_RX_LPI_TIME)

0B8h

Host MAC TX LPI Transitions Register (HMAC_TX_LPI_TRANSITION)

0BCh

Host MAC TX LPI Time Register (HMAC_TX_LPI_TIME)

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