LAN9250 datasheet(185/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 185

LAN9250

11.14.8

HOST MAC CSR INTERFACE COMMAND REGISTER (MAC_CSR_CMD)

This read-write register is used to control the read and write operations to/from the Host MAC. This register in used in

conjunction with the Host MAC CSR Interface Data Register (MAC_CSR_DATA) to indirectly access the Host MAC

CSRs.

Note:

The full list of Host MAC CSRs are described in Section 11.15, "Host MAC Control and Status Registers,"

on page 192.

Offset:

0A4h

Size:

32 bits

Bits

Description

Type

Default

Host MAC CSR Busy (HMAC_CSR_BUSY)

When a 1 is written into this bit, the read or write operation is performed to

the specified Host MAC CSR. This bit will remain set until the operation is

complete. In the case of a read, this indicates that the host can read valid

data from the Host MAC CSR Interface Data Register (MAC_CSR_DATA).

Note:

The MAC_CSR_CMD and MAC_CSR_DATA registers must not be

modified until this bit is cleared.

R/W

R/nW

When set, this bit indicates that the host is requesting a read operation.

When clear, the host is performing a write.

0: Host MAC CSR Write Operation

1: Host MAC CSR Read Operation

R/W

29:8

RESERVED

7:0

CSR Address

The 8-bit value in this field selects which Host MAC CSR will be accessed by

the read or write operation. The index of each Host MAC CSR is defined in

Section 11.15, "Host MAC Control and Status Registers," on page 192.

R/W

00h

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