LAN89730 datasheet(34/218 Pages) MICROCHIP

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LAN89730

DS60001348A-page 34

 2013-2015 Microchip Technology Inc.

4.3.1.3

Endpoint 3 (Interrupt)

The Interrupt Endpoint is responsible for indicating device status at each polling interval. The Interrupt Endpoint is imple-

mented via the CTL module. When the Endpoint is accessed, the Interrupt packet specified in Table 4-2 is presented to

the host.

If there is no interrupt status to report, the device responds with a NACK.

The interrupt status can be cleared by writing to Interrupt Status Register (INT_STS).

4.3.1.4

Endpoint 0 (Control)

The Control Endpoint is handled by the CTL (USB Control) module. The CTL module is responsible for handling USB

standard commands, as well as USB vendor commands. In order to support these commands, the CTL must compile

a variety of statistics and store the programmable portions of the USB descriptors. The supported USB commands can

be found in Section 4.3.2, "USB Standard Commands".

TABLE 4-2:

INTERRUPT PACKET FORMAT

Bits

Description

31:20

RESERVED

MACRTO_INT

RX FIFO Has Frame. The RX FIFO has at least one complete Ethernet frame.

TXSTOP_INT

RXSTOP_INT

PHY_INT

TXE

TDFU

TDFO

RXDF_INT

10:0

GPIO_INT

Note:

The polling interval is static and set through the EEPROM. The host can change the polling interval by

updating the contents of the EEPROM and resetting the part.

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